zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 88

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

11.5
11.6
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
11.6.1
TDM_CLKiP High / Low
Pulsewidth
TDM_CLKiS High / Low
Pulsewidth
TXCLK period
TXCLK high time
TXCLK low time
TXCLK rise time
TXCLK fall time
TXCLK rise to TXD[3:0] active
delay (TXCLK rising edge)
TXCLK to TXEN active delay
(TXCLK rising edge)
PAC Interface Timing
Packet Interface Timing
TDM_RXDATA
TDM_TXDATA
TDM_RXCLK
TDM_TXCLK
MII Transmit Timing
Parameter
Parameter
Figure 33 - TDM-LIU Structured Transmission/Reception
Table 35 - MII Transmit Timing - 100 Mbps
Symbol
Table 34 - PAC Timing Specification
t
t
t
CLO
t
t
t
t
CHI
CC
CR
DV
Symbol
CF
EV
t
t
CPP
CSP
ZL50110/11/12/14
t
Zarlink Semiconductor Inc.
S
Min.
14
14
1
1
Min.
-
-
-
10
10
t
t
CRP
CTP
88
100 Mbps
Typ.
Typ.
40
-
-
t
t
t
-
-
-
-
-
-
CTH
CRH
PD
t
H
Max.
-
-
Max.
26
26
25
25
5
5
-
t
t
CTL
CRL
Units
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
Load = 25 pF
Load = 25 pF
Data Sheet
Notes
Notes