zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 47

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

3.6
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock. No chip access should occur at this time.
SYSTEM_CLK
SYSTEM_RST
SYSTEM_DEBUG
System Function Interface
Signal
Table 16 - System Function Interface Package Ball Definition
I/O
I
I
I
U6
V4
U5
ZL50110/11/12/14
Package Balls
Zarlink Semiconductor Inc.
47
System Clock Input. The system clock
frequency is 100 MHz. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the
ZL50110/11/12/14 to be reset to their
default state. Recommend external
pull-up.
System Debug Enable. This is an
asynchronous signal that, when
de-asserted, prevents the software
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
Description
Data Sheet