zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 33

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

Note: Mn can be either M0, M1, M2, or M3 for ZL50111 and ZL50112 variants; and M0 or M1 for ZL50110 variant.
M_MDC
M_MDIO
Signal
OT
I/O
ID/
Mn_RXD[3:0]
O
Mn_TXD[3:0]
Table 9 - MII Management Interface Package Ball Definition
Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI
Mn_TXCLK
Mn_RXDV
Mn_RXER
Mn_TXEN
Mn_TXER
Mn_COL
Mn_CRS
MII
H23
G26
-
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Mn_GTX_CLK
Mn_RXD[7:0]
Mn_TXD[7:0]
Mn_RXDV
Mn_RXER
Mn_TXEN
Mn_TXER
Mn_CRS
Mn_COL
GMII
33
-
MII management data clock. Common for all
four MII ports. It has a minimum period of
400 ns (maximum freq. 2.5 MHz), and is
independent of the TXCLK and RXCLK.
MII management data I/O. Common for all
four MII ports at up to 2.5 MHz. It is
bi-directional between the ZL50110/11/12/14
and the Ethernet station management entity.
Data is passed synchronously with respect
to M_MDC.
Mn_Signal_Detect
Mn_GTX_CLK
Mn_RXD[7:0]
Mn_TXD[7:0]
Mn_RXD[8]
Mn_RXD[9]
Mn_TXD[8]
Mn_TXD[9]
TBI (PCS)
Mn_RBC1
-
Description
Data Sheet