zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 66
zl50110gag2
Manufacturer Part Number
zl50110gag2
Description
1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50110GAG2.pdf
(110 pages)
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6.3
The quality of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive
clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator.
Please review application note ZLAN-153 “External Component Selection” before choosing an oscillator.
SYSTEM_CLK Considerations
Source
Clock
ZL5011x
source
node
Figure 19 - Adaptive Clock Recovery
Packets
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Network
66
Packets
ZL5011x
destination
node
Queue
Stamp
Host CPU
Time
monitor
Queue
DCO
Dest'n
Clock
Data Sheet
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