zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 72

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zl50011

Manufacturer Part Number
zl50011
Description
Flexible 512 Channel Dx With On-chip Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
AC Electrical Characteristics - Input and Output Frame Boundary Alignment
1
2
Input and Output Frame Offset in
DPLL Master Mode
Input and Output Frame Offset in
DPLL Bypass Mode
CKo2 or FPo1
CKo1 or CKo0
(16.384MHz)
FPo2 or FPo1
Input Frame Boundary
FPo1 or FPo0
(4.096MHz)
(8.192MHz)
(16.384MHz)
(32.768MHz)
(4.096MHz)
(8.192MHz)
CKo2
CKo0
CKi
CKi
FPo2
FPi
CKi
FPi
FPo0
FPi
Characteristic
Figure 39 - Input and Output Frame Boundary Offset
t
FBOS
Zarlink Semiconductor Inc.
Sym.
t FBOS
t FBOS
Output Frame Boundary
ZL50011
72
Min.
-20
1
Typ.
Max.
18
0
Units
ns
ns
Input reference is internal
8 kHz derived from FPi
and CKi.
Measured when there is
no jitter on the CKi and
FPi inputs.
Measured when there is
no jitter on the CKi and
FPi inputs.
Notes
Data Sheet

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