zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 29

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

When the input channel delay and the output channel delay are enabled, the data throughput delay is: T = 3 frames
- α + β + (m-n). Figure 24 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
2.5
The connection memory is 12-bit wide. There are 512 memory locations to support the ST-BUS serial outputs
STo0-15. The address of each connection memory location corresponds to an output destination stream number
and an output channel number. See Table 32 on page 64 for the connection memory address map.
When Bit 0 of the connection memory is low, Bit 1 to 7 define the source (input) channel address and Bit 8 to 11
define the source (input) stream address. Once the source stream and channel addresses are programmed by the
microprocessor, the contents of the data memory at the selected address are switched to the mapped output
stream and channel. See Table 33 on page 65 for details on the memory bit assignment when Bit 0 of the
connection memory is low.
When Bit 0 of the connection memory is high, Bit 1 and 2 define the per-channel control modes of the output
streams, the per-channel high impedance output control, the per-channel message and the per-channel BER test
modes. In the message mode, the 8-bit message data located in Bit 3 to 10 of the connection memory will be
transferred directly to the mapped output stream. See Table 34 on page 65 for details on the memory bit
assignment when Bit 0 of the connection memory is high.
2.5.1
This feature allows fast initialization of the entire connection memory after power up. When block programming
mode is enabled, the content of Bit 1 to 3 in the Internal Mode Selection (IMS) Register will be loaded into Bit 0 to 2
of all the 512 connection memory locations. The other bit positions of the connection memory will be loaded
with zeros.
Figure 24 - Data Throughput Delay when Input and Output Channel Delay are Enabled for Input
Connection Memory Description
Serial Output Data
Serial Output Data
Serial Input Data
Serial Input Data
Connection Memory Block Programming
Frame
(α = 1)
(α > 1)
(β = 1)
(β > 1)
Frame N-1 Data
Frame N Data
Frame N-3 Data
Frame N
Frame N-4 Data
3 Frames - 1 + β + 0
Input Channel Delay:(from 1 to max# of channels, programmed by the STIN#CD6-0 bit)
Frame N+1 Data
Frame N Data
Frame N-2 Data
Frame N+1
3 Frames - 1 + 1 + 0
Frame N-3 Data
Ch0 Switched to Output Ch0
Zarlink Semiconductor Inc.
ZL50011
3 Frames - α + 1 + 0
Frame N+1 Data
Frame N+2 Data
Frame N-1 Data
Frame N+2
Frame N-2 Data
29
Frame N+2 Data
Frame N+3 Data
Frame N+3
Output Channel Delay:(from 1 to max# of channels,
programmed by the STO#CD6-0 bit)
Frame N-1 Data
Frame N Data
3 Frames - α + β + 0
Frame N+3 Data
Frame N+4 Data
Frame N+1 Data
Frame N+4
Frame N Data
Frame N+4 Data
Frame N+4 Data
Frame N+5 Data
Frame N+2 Data
Frame N+5
Frame N+1 Data
Data Sheet