zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 34

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

2.9.3
DPLL Bypass mode is selected by setting high bit 14 of the Control Register (CR), as shown in Table 14. The DPLL
is completely bypassed and the APLL takes its input from CKi instead of the oscillator. The APLL multiplies the
ST-BUS input clock CKi with an appropriate frequency multiplication factor to generate the internal clock MCKTDM.
MCKTDM is synchronized to CKi. MCKTDM provides timing for the TDM switching function and for the ST-BUS
outputs. Hence the ST-BUS outputs are synchronized to CKi. The DPLL intrinsic jitter will not be added onto the
ST-BUS outputs because the DPLL is completely bypassed.
In this mode, the APLL takes its input from CKi instead of the oscillator. If the device is to be used in this mode only,
external 20 MHz oscillator is not required, but the XTALi pin should still get a valid clock signal so that the device
can be initialized. The easiest way is to tie the CKi clock to the XTALi pin. The XTALo pin must be left unconnected.
Bypass mode is used when another device, such as another ZL50011 in Master mode, is providing system timing.
2.10
Figure 25 shows the functional block diagram of the DPLL. Major functional blocks are described in the following
sections. When the DPLL is in Master or Freerun mode, the APLL input is C20i from the oscillator and the APLL
multiplies C20i to generate the DPLL master clock MCKDPLL.
2.10.1
The ST-BUS input frame pulse (FPi) is sampled with the ST-BUS input clock (CKi) inside the CKi/FPi synchronizer
to create the 8 kHz reference CKi/FPi. Either CKi/FPi or REF is selected by the reference select bit (P_REFSEL in
the DOM register) as the REF_INT input to the Skew Control Circuit.
CKi
FPi
DPLL Functional Description
(P_REFSEL bit in DOM)
DPLL Bypass Mode
REF
CKi/FPi Synchronizer and REF Select Mux
C20i
CKi/FPi
Synchronizer
(Selected by FP0-1 bits in DOM)
P_REFSEL
(SKC0-2 bits in DPOA)
SKEW_CONTROL
APLL
FREQ_MOD
Select
MUX
REF
MCKDPLL
Figure 25 - DPLL Functional Block Diagram
Reference
Monitor
REF_INT
Zarlink Semiconductor Inc.
ZL50011
34
(FREERUN bit in DOM)
(POS0-6 bits in DPOA)
(Fig. 25)
FAIL_REF
Control
Skew
PHASE_OFFSET
RESET Pin
FREERUN
FREQ_MOD
REF
(See Fig.26)
PLL
Data Sheet
MCKTDM
FRAME