zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 32

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

2.8
The device supports the non-multiplexed microprocessor. The microprocessor port consists of a 16-bit parallel data
bus (D0 to 15), a 12-bit address bus (A0 to 11) and four control signals (CS, DS, R/W and DTA). The parallel
microprocessor port provides fast access to the internal registers, the connection and the data memories.
The 512 connection memory locations can be read or written via the 16-bit microprocessor port. On the other hand,
the 512 data memory locations can only be read (but not written) from the microprocessor port.
For the connection memory write operation, D0 to 11 of the data bus will be used and D12 to 15 are ignored (D12 to
15 should be driven low). For the connection memory read operation, D0 to D11 will be used and D12 to D15 will
output zeros. For the data memory read operation, D0 to D7 will be used and D8 to D15 will output zeros.
See Table 32 on page 64 for the address mapping of the data memory. Refer to Figure 47 on page 79 for the
microprocessor port timing.
2.9
The DPLL meets the requirements of Telcordia GR-1244-CORE Stratum 4 specifications (Stratum 4). It can be set
into one of three operating modes: Master, Freerun or Bypass.
The input streams STi0-15 are always sampled with the ST-BUS input clock CKi. The ST-BUS input frame pulse
FPi denotes the input frame boundary. The objective of the DPLL is to generate the high-speed internal clock
MCKTDM (see Figure 25 on page 34). MCKTDM provides timing for the TDM switching function and timing for the
ST-BUS outputs. (In this context CKo0-2, FPo0-2, STo0-15 and STOHZ0-15 are collectively known as the ST-BUS
outputs.)
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In Master mode, the DPLL synchronizes to the input timing reference to generate the internal clock
MCKTDM. Typically the timing reference is from the network. The DPLL provides jitter attenuation function.
The Master mode ST-BUS output clocks and frame pulses are synchronized to the network reference and
can be used as a system’s ST-BUS timing source.
In Freerun mode, the DPLL is not synchronized to the timing reference. It synthesizes the internal clock
MCKTDM based on the oscillator clock. Typically Freerun mode is used when a system’s timing is
independent of the network. In that case, the Freerun mode ST-BUS output clocks and frame pulses must be
used as the system’s ST-BUS timing source.
In Bypass mode, the DPLL is completely bypassed. The Analog Phase-Locked Loop (APLL) synchronizes to
the ST-BUS input clock CKi to generate the internal clock MCKTDM. Bypass mode is used when the
system’s ST-BUS timing is supplied by another device, e.g. another ZL50011 in Master mode.
Microprocessor Port
Digital Phase-Locked Loop (DPLL) Operation
STIN#QEN2
STIN#QEN3
1
0
1
0
Table 13 - Quadrant Frame 3 LSB Replacement
Table 12 - Quadrant Frame 2 LSB Replacement
Replace LSB of every channel in Quadrant 2 with "1"
No bit replacement occurs in Quadrant 2
Replace LSB of every channel in Quadrant 3 with "1"
No bit replacement occurs in Quadrant 3
Zarlink Semiconductor Inc.
ZL50011
32
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