zl50011 Zarlink Semiconductor, zl50011 Datasheet - Page 48

• Manufacturer Part Number: zl50011
• Description: Flexible 512 Channel Dx With On-chip Dpll
• Manufacturer: Zarlink Semiconductor

2 - 0
External Read/Write Address: 000
Reset Value: 0000
Bit
MODE
6
5
4
3
FBD
15
SLV
14
MS2-0
MBPE
Name
CBER
SBER
OSB
FBD
13
EN
H
CKIN
Bit Error Rate Counter Clear: When this bit is high, it resets the internal bit error counter
and the content of the bit error count register (BCR) to zero. Upon completion of the
reset, set this bit to zero.
Bit Error Rate Test Start: When this bit is high, it enables the BER transmitter and
receiver; starts the bit error rate test. The bit error test result is kept in the bit error count
(BCR) register. Upon the completion of the BER test, set this bit to zero.
Memory Block Programming Enable: When this bit is high, the connection memory
block programming mode is enabled to program Bit 0 to 2 of the connection memory.
When it is low, the memory block programming mode is disabled.
Output Stand By Bit: This bit enables the STo0 - 15 and the STOHZ 0 -15 serial outputs.
following table describes the HiZ control of the serial data outputs:
Memory Select Bit. These bits are used to select connection memory or data memory:
12
2
Table 16 - Control Register (CR) Bits (continued)
CKIN
11
1
H
CKIN
10
0
010 - 111
RESET
MS2 - 0
Pin
CKFP
000
001
0
1
1
1
9
2
Zarlink Semiconductor Inc.
ZL50011
CKFP
ODE
Pin
8
1
X
0
1
1
48
CKFP
OSB
Connection Memory Read/Write
7
0
Bit
X
X
0
1
Description
Data memory Read
CBER
Memory Selection
6
STo0-15
Active
HiZ
HiZ
HiZ
Reserved
SBER
5
STOHZ 0-15
Driven High
Driven High
Driven High
MBPE
Active
4
OSB
3
MS2
2
Data Sheet
MS1
1
The
MS0
0