mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 73

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

When the pre-processing option is enabled, (using the RX Cell Processor Enable register), the IRQ normally
generated to indicate that a new cell was put in the RX Cell buffer is re-defined to indicate that the compare process
has been complete and that the bytes that were found to be different are available for the software to access, in the
link Preprocessor FIFO.
For each link, the FIFO is 64 words deep to accommodate up to 64 preprocessed bytes (bytes that were found to be
different). The bytes in the FIFO can be from different preprocessed cells.
Whenever bit 14 of the word read from the FIFO is set, indicating the last byte of an ATM cell, the software has to
check the level of bit 15 to determine if there are more bytes to be read from other processed cells on the same link.
If there are no more bytes, then the software should start polling the status bit (empty/not empty) and/or wait for an
IRQ before reading the FIFO. To facilitate this task, associated with the RX Cell FIFOs, the Processed RX Cell Link
FIFO Status register (0x107) reports if a FIFO is empty or not empty. Each bit in the register is reflecting the status
of one of the sixteen links.
When the preprocessing option is not enabled, the RX Cell buffers operate the same way as in the MT90220/221.
All 53 bytes from the ATM Cell are accessible when the preprocessing mode is disabled and the preprocessor FIFO
are not used.
6.5
The TDM Ring Block is typically used to form IMA groups that source their links from more than one MT90222/3/4.
All MT90222/3/4 devices in the TDM Ring must operate synchronously, with the same system clock. This system
clock needs to be the identical in frequency but not necessarily phase aligned.
The TDM Ring is located between the TDM Serial Interface (S/P converters) and the internal Transmission Control
(TC) / IMA blocks (see figures 3 and 7). This bus allows links to be routed from one MT90222/3/4 to other
MT90222/3/4s as if the link was internally sourced, limited by the MT90224’s link capacity of 16 links (8 links on the
MT90223 and 4 links on the MT90222) and the TDM Ring capacity of 32 links.
Operation of the TDM Ring is programmed via 16 Ring Tx Link (0x0181-0x0190) registers, 16 Ring Rx Link
(0x01C0-0x01CF) registers and one Ring Tx Control (0x0180) register.
The Ring Tx Control (0x0180) sets which MT90222/3/4 is the master (source of the TDM Ring clock) and whether
the TDM Ring is active (not tri-stated). There can be only one TDM Ring master in a single ring. A link is then placed
on the ring by associating it with one available time slot and then retrieved off the ring by referencing the same time
slot.
See Technical Note TN90224.1 for more information.
TDM Ring Block
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Processed RX Cell FIFO Word Format
Figure 19 - Processed RX Cell FIFO Word Format
Zarlink Semiconductor Inc.
MT90222/3/4
73
Byte content from the latest RX Cell
Position in Cell for the byte found to be
different (number range between 1 and 51)
When set, indicates the last byte reported
for the current processed cell.
When clear (0), indicates that the FIFO associated with
this link is empty (no more bytes to be read)
Data Sheet