mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 122

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
15:0
6:5
4:3
8
7
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
Digital Loopback mode
When 1, loopback mode, RXCK, RXSYNC and DSTi come from the TX pins of the same
link. Both TX and RX blocks operate normally.
When 0, normal mode, RXCK, RXSYNC and DSTi come from the RX pins of the link
Link enable:
0: RX Port is not active
1: RX port is active
Data rate:
11: 8.192 Mb/sec.
10: 4.096 Mb/sec.
01: 2.048 Mb/sec
00: 1.544 Mb/sec
Multiplex mode select:
00: no demultiplexing,
01: demultiplex on a per byte basis, 1 link to 2 links. Valid only for ST-BUS mode when
TxCK and TxSYNC are inputs.
10: demultiplex on a per byte basi
s, 1 link to 4 links. Valid only for ST-BUS mode when TxCK and TxSYNC are inputs.
Clock and sync format:
When 0, TDM is in Generic mode: clock is 1x data rate and sync is 1 bit long at beginning
of frame.
When 1, TDM is ST-BUS Format: clock 2x data rate and sync as per ST-BUS format
Clock polarity:
When 0, the data is sampled at the rising edge of RXCK
When 1, the data is sampled at the falling edge of RXCK
This bit is ignored in ST-BUS Format.
Sync polarity:
When 0, the sync pulse is active low
When 1, the sync pulse is active high.
This bit is ignored in ST-BUS Format.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTi pin is ignored for the corresponding time slot
This registers controls time slots 15:0.
0x0700 - 0x070F (16 reg)
1 reg. per RX link.
0000
0x0710 - 0x071F (16 reg)
Control time slot 15:0.
0000
Table 109 - TDM RX Mapping (timeslots 15:0) Register
Table 108 - TDM RX Link Control Register (continued)
Zarlink Semiconductor Inc.
MT90222/3/4
122
Description
Description
Data Sheet