mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 130
mt90224
Manufacturer Part Number
mt90224
Description
8-port Ima/tc Phy Device
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90224.pdf
(155 pages)
- Current page: 130 of 155
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8.2.1
For MT90224, the following modes of operation must be selected and programmed:
Serial stream mode of up to 2.5 Mb/s per link.
TxCK is configured as input.
Recommended register settings:
TDM Tx Link Control Register (0x600 – 0x60F)
TDM Tx Mapping Registers
TDM Tx Mapping Registers
TDM Rx Link Control Register (0x700 – 0x70F)
TDM Rx Mapping Registers
TDM Rx Mapping Registers
Rx Automatic Synchronization Register (0x741) should be set to 0x0036
Orion chipset provides both TxCLK and RxCLK to MT90224.
Orion chipset should be configured in serial interface mode.
Zarlink’s MSAN - 208 Application note describes the IMA to G.SHDSL connection in detail and also contains the
reference design of the interface.
For detailed programming of Orion chipset, please refer to Globespan’s application note AN-073.
Modes of Operation
(0x710 – 0x71F)
(0x720 – 0x72F)
(0x610 – 0x61F)
(0x620 – 0x62F)
Zarlink Semiconductor Inc.
MT90222/3/4
should be set to 0x02A3.
should be set to 0x04A3.
should be set to 0xFFFF.
should be set to 0xFFFF.
should be set to 0xFFFF.
should be set to 0xFFFF.
130
Data Sheet
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