mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 22

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

MT90223 Pin Description (continued)
AA24,
Pin #
AC26
AE21
AE19
AD17
AA26
AF21
AD26,
AD20,
AD18,
AD16
W23,
AC25
AF19
AF17
W25
W24
T25,
V25,
R23
U25
M26
G25
U24
M25
G23
D26
C21
N24
G26
C23
C20
Y23
E26
A25
A22
B20
T26
K26
B24
A20
F24
B22
L24
J23
J24
L25
J25
TXSYNCio
RXSYNCi
TXCKio
Name
RXCKi
DSTo
DSTi
[14]
[12]
[10]
[14]
[12]
[10]
[14]
[12]
[10]
[14]
[12]
[10]
[14]
[12]
[10]
[14]
[12]
[10]
[8]
[6]
[4]
[2]
[0]
[8]
[6]
[4]
[2]
[0]
[8]
[6]
[4]
[2]
[8]
[6]
[4]
[2]
[0]
[8]
[6]
[4]
[2]
[0]
[8]
[6]
[4]
[2]
[0]
[0
I/O
I/O TDM Interface Transmit Clock. This pin is an input or an output as selected by the
I/O Transmit Line Frame Pulse. This pin is an input or an output as selected by the TDM
O Serial TDM Data Output. Serial stream which contains transmit data. The output is
I
I
I
set to high impedance for unused time slots and if the link is not used. It is aligned
with TXCKio and TxSYNCio.
Serial TDM Data Input. Serial stream which contains receive data. It is aligned with
RXCKi and RxSYNCi. These pins have internal weak pull-downs.
TDM TX Link Control registers. The TXCK source is software selectable and can be
either one of the eight RXCK or one of the four REFCK signals when defined as
output. When defined as input, the proper clock signal is provided to the input pin. The
clock polarity is determined by the TDM TX Link Control registers. These pins have
internal weak pull-downs.
TX Link Control registers.
It is the frame reference (typically 8 kHz) used as transmit synchronization for the
TDM system interface. When an output, the TXSYNC is generated from the TXCK
signal and is independent from other TXSYNC signals. Two major modes are
available: generic and ST-Bus:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32/64/128
channel frame of the ST-BUS interface at DSTi and DSTo lines.
2. For generic TDM Interfaces, it can be programmed to generate or receive either a
positive or negative pulse polarity that marks the first bit of the TDM system interface.
These pins have internal weak pull-downs.
Receive line Frame Pulse. It is the frame reference (typically 8 kHz) used as receive
synchronization for the TDM system interface. Two major modes are available:
generic and ST-Bus:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32/64/128
channel frame of the ST-BUS interface at DSTi and DSTo lines.
2. For generic TDM Interfaces, it can be programmed to accept either a positive or
negative pulse polarity that marks the first bit of the TDM system interface. These pins
have internal weak pull-downs.
TDM Interface Receive Clock. This input line represents the clock for the receive
serial TDM data. The expected frequency value to be received at this input clock is
defined by the user through the RX Link TDM Control register. These pins have
internal weak pull-downs.
Zarlink Semiconductor Inc.
TDM Interface Signals
MT90222/3/4
22
Description
Data Sheet