mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 141

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mt90224

Manufacturer Part Number
mt90224
Description
8-port Ima/tc Phy Device
Manufacturer
Zarlink Semiconductor
Datasheet
AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
1
2
3
4
5
UP_AD[11:0]
UP_D[15:0]
UP_R/W set-up time to UP_CS
falling edge
Address and Data set up before
rising edge of UP_CS
UP_AD and Data hold time after
UP_CS rising edge
UP_R/W low after rising edge or
UP_CS
UP_CS high before next UP_CS
low
UP_R/W
UP_OE
UP_CS
Characteristics
t
ws
Figure 33 - CPU Interface Motorola Timing - Write Access
Sym.
t
t
t
t
ADH
CSH
t
WH
WS
SU
Zarlink Semiconductor Inc.
MT90222/3/4
(see Note 1)
141
Address Valid
Min.
Data Valid
10
1
4
1
2
t
su
Typ.
t
wh
Max.
t
adh
t
csh
system
Units
cycle
clock
ns
ns
ns
ns
Test Conditions
Data Sheet

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