zl30410 Zarlink Semiconductor, zl30410 Datasheet - Page 6

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zl30410

Manufacturer Part Number
zl30410
Description
Multi-service Line Card Pll
Manufacturer
Zarlink Semiconductor
Datasheet

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Pin Description
Pin #
7, 8
2-5
10
11
12
13
14
15
16
17
18
19
20
1
6
9
Name
C16o
GND
GND
F16o
VDD
MS1
MS2
FCS
C8o
C4o
C2o
F0o
F8o
NC
NC
IC
Internal Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Ground. Negative power supply.
No internal bonding Connection. Leave unconnected.
Filter Characteristic Select (Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30410. Set this pin high to have a loop filter
corner frequency of 6 Hz and limit the phase slope to 41 ns per 1.326 ms. Set
this pin low to have corner frequency of 12 Hz with no phase slope limiting
imposed. This pin is internally pulled down to GND.
Positive Power Supply
Ground
Frame Pulse ST-BUS 8.192 Mbps (CMOS tristate output). This is an 8 kHz,
61 ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mbps.
Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mbps.
Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mbps.
Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mbps.
Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mbps.
Frame Pulse ST-BUS 2.048 Mbps (CMOS tristate output). This is an 8 kHz,
244 ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mbps and
4.096 Mbps.
Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 16 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 16 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Frame Pulse ST-BUS/GCI 8.192 Mbps (CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at
8.192 Mbps. See Figure 15 for details.
Zarlink Semiconductor Inc.
ZL30410
6
Description
Data Sheet
.

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