zl30410 Zarlink Semiconductor, zl30410 Datasheet - Page 10

• Manufacturer Part Number: zl30410
• Description: Multi-service Line Card Pll
• Manufacturer: Zarlink Semiconductor

3.0
The ZL30410 is designed to provide timing for SDH and SONET equipment conforming to ITU-T, ANSI, ETSI and
Telcordia recommendations. In addition, it generates clocks for SDH and PDH equipment operating at DS1, DS2,
DS3, E1, and E3 rates. The ZL30410 provides clocks for industry standard ST-BUS and GCI backplanes, and it
also supports H.110 timing requirements. The functional block diagram of the ZL30410 is shown in Figure 1,
“Functional Block Diagram,” on page 1 and its operation is described in the following sections.
3.1
The ZL30410 has two Acquisition PLLs for monitoring availability and quality of the Primary (PRI) and Secondary
(SEC) reference clocks. Each Acquisition PLL operates independently and locks to the falling edges of one of the
three input reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz or to the rising edge of 19.44 MHz. The reference
frequency is automatically detected by the ZL30410 device.
The Primary and Secondary Acquisition PLLs are designed to provide indication of two levels of reference clock
quality. For clarity, only the Primary Acquisition PLL is referenced in the text, but the same applies to the Secondary
Acquisition PLL:
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Outputs of both Acquisition PLLs are connected to a multiplexer (MUX), which allows selection of the desired
reference. This multiplexer channels binary words to the Core PLL digital phase detector (instead of analog signals)
which eliminates quantization errors and improves phase alignment accuracy. The bandwidth of the Acquisition
PLL is much wider than the bandwidth of the following Core PLL. This feature allows cascading Acquisition and
Core PLLs without altering the transfer function of the Core PLL.
3.2
The most critical element of the ZL30410 is its Core PLL, which generates a phase-locked clock, filters jitter and
suppresses input phase transients. All of these features are in agreement with international standards:
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When locked to a G.813 Option 1 and 2 or SONET Stratum 3 quality clock the ZL30410 generates clocks that also
meet SONET Stratum 3 or G.813 Option 1 and 2 requirements.
The Core PLL supports three mandatory modes of operation: Free-run, Normal (Locked) and Holdover. Each of
these modes places specific requirements on the building blocks of the Core PLL.
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Some of the key elements of the Core PLL are shown in Figure 3 "Core PLL Functional Block Diagram".
Reference frequency drifts more than ±12 ppm. In response, the PRIOR (Primary Reference Out of Range)
pin changes state to high, in conformance with Stratum 3 requirements defined in GR-1244-CORE
Reference frequency drifts more than ±30000 ppm or that the reference has been lost completely. In
response, the Primary Acquisition PLL enters its own Holdover mode which forces the Core PLL into the
Auto Holdover state.
G.813 Option 1 clocks for SDH equipment
GR-1244 for Stratum 4E and 4 Clocks
In Free-run Mode, the Core PLL derives its output clock from the 20 MHz Master Clock Oscillator connected
to pin C20i. The stability of the generated clocks remains the same as the stability of the Master Clock
Oscillator.
In Normal Mode, the Core PLL locks to one of the Acquisition PLLs. Both Acquisition PLLs provide
preprocessed phase data to the Core PLL including detection of reference clock quality.
In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The
Core PLL enters Holdover mode if the attached Acquisition PLL switches into the Holdover state or under
external control.
Acquisition PLLs
Core PLL
Functional Description
Zarlink Semiconductor Inc.
ZL30410
10
Data Sheet