spt9712 Fairchild Semiconductor, spt9712 Datasheet - Page 4

• Manufacturer Part Number: spt9712
• Description: 12-bit, 100 Mwps Ecl D/a Converter
• Manufacturer: Fairchild Semiconductor

THEORY OF OPERATION
The SPT9712 uses a segmented architecture incorporat-
ing most significant bit (MSB) decoding. The four MSBs
(D1–D4) are decoded to thermometer code lines to drive
15 discrete current sinks. For the eight least significant
bits (LSBs), D5 and D6 are binary weighted and D7–D12
are applied to the R-2R network. The 12-bit decoded data
is input to internal master/slave latches. The latched data
is input to the switching network and is presented on the
output pins as complementary current outputs.
TYPICAL INTERFACE CIRCUIT
The SPT9712 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
SPT9712 in normal circuit operation. The following sec-
tions provide descriptions of the pin functions and outline
critical performance criteria to consider for achieving opti-
mal device performance.
POWER SUPPLIES AND GROUNDING
The SPT9712 requires the use of a single –5.2 V supply.
All supplies should be treated as analog supply sources.
This means the ground returns of the device should be
connected to the analog ground plane. All supply pins
should be bypassed with .01 µF and 10 µF decoupling
capacitors as close to the device as possible.
The two grounds available on the SPT9712 are DGND
and AGND. These grounds are not tied together internal to
the device. The use of ground planes is recommended to
achieve the best performance of the SPT9712. All ground,
reference and analog output pins should be tied directly to
the DAC ground plane. The DAC and system ground
planes should be separate from each other and only con-
nected at a single point through a ferrite bead to reduce
ground noise pickup.
DIGITAL INPUTS AND TIMING
The SPT9712 uses single-ended, 10K ECL-compatible
inputs for data inputs D1–D12 and Latch Enable. It also
employs master/slave latches to simplify digital interface
timing requirements and reduce glitch energy by synchro-
nizing the current switches. This is an improvement over
the AD9712, which typically requires external latches for
digital input synchronization.
Referring to figure 1, data is latched into the DAC on the
rising edge of the latch enable clock with the associated
setup and hold times. The output transition occurs after a
typical 1 ns propagation delay and settles to within ±1 LSB
in typically 13 ns. Because of the SPT9712’s rising-edge
triggering, no timing changes are required when replacing
an AD9712 operating in the transparent mode.
4
VOLTAGE REFERENCE
When using the internal reference, Ref Out should be con-
nected to Control Amp In and decoupled with a 0.1 µF
capacitor. Control Amp Out should be connected to Ref In
and decoupled to the analog supply. (See figure 2.)
Full-scale output current is determined by Control Amp In
and R
The internal reference is typically –1.20 V with a tolerance
of ±0.05 V and a typical drift of 50 ppm/°C . If greater accu-
racy or temperature stability is required, an external refer-
ence can be utilized.
OUTPUTS
The output of the SPT9712 is comprised of complemen-
tary current sinks, I
at either I
The sum of the two is always equal to the full-scale output
current minus one LSB.
By terminating the output current through a resistive load
to ground, an associated voltage develops. The effective
resistive load (R
(R
which develops can be determined using the following
formulas:
The resistive load of the SPT9712 can be modified to in-
corporate a wide variety of signal levels. However, optimal
device performance is achieved when the outputs are
equivalently loaded.
Out
Control Amp Out = –1.2 V, and R
I
R
R
R
V
Out
) in parallel with the resistive load (R
Out
L
Out
Eff
Set
= 51
(FS) = (–1.2 V / 7.5 k ) x 128 = –20.48 mA
I
(Current Out is a constant 128 factor of the
reference current)
= 51
Out
= R
= 1.0 k
using the following formula:
Out
(FS) = (Control Amp In / R
Eff
or I
x I
Out
|| 1.0 k
Eff
Out
) is the output resistance of the device
Out
are based upon the digital input code.
(FS) = 48.52
and I
= 48.52
= –0.994 V
Out
. The output current levels
Set
x –20.48 mA
Set
= 7.5 k
) x 128
L
). The voltage
SPT9712
2/15/01