huf76409d3s Fairchild Semiconductor, huf76409d3s Datasheet - Page 8

• Manufacturer Part Number: huf76409d3s
• Description: 17a, 60v, 0.071 Ohm, N-channel, Logic Level Ultrafet Power Mosfet
• Manufacturer: Fairchild Semiconductor

SABER Electrical Model
REV 23 August 1999
template huf76409d n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.84e-13, cjo = 6.40e-10, tt = 5.10e-8, xti = 4.35, m = 0.52)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 3.70e-10, is = 1e-30, m = 0.79)
m..model mmedmod = (type=_n, vto = 2.08, kp = 3.2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.40, kp = 28, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.80, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -2.8)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.8, voff = -5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
c.ca n12 n8 = 6.30e-10
c.cb n15 n14 = 6.30e-10
c.cin n6 n8 = 4.60e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 3.73e-9
l.lsource n3 n7 = 3.43e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.13e-3, tc2 = -3.00e-7
res.rdbody n71 n5 = 1.56e-2, tc1 = -1.0e-3, tc2 = 7.00e-6
res.rdbreak n72 n5 = 3.70e-1, tc1 = 9.10e-4, tc2 = -1e-6
res.rdrain n50 n16 = 1.88e-2, tc1 = 9.80e-3, tc2 = 2.85e-5
res.rgate n9 n20 = 3.76
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 37.3
res.rlsource n3 n7 = 34.3
res.rslc1 n5 n51= 1e-6, tc1 = 5.00e-3, tc2 = 5.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.40e-2, tc1 = 1.5e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.68e-3, tc2 = 8.00e-7
res.rvthres n22 n8 = 1, tc1 = -1.48e-3, tc2 = -8.30e-6
spe.ebreak n11 n7 n17 n18 = 66.55
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/43))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
5
MSTRO
14
51
21
RDRAIN
RSLC1
50
ISCL
16
8
MMED
8
RDBREAK
DBREAK
IT
RSOURCE
MWEAK
17
EBREAK
RVTHRES
RBREAK
72
11
+
-
17
18
HUF76409D3, HUF76409D3S Rev. B
7
+
-
18
22
RVTEMP
19
71
RLSOURCE
RLDRAIN
LSOURCE
VBAT
RDBODY
DBODY
LDRAIN
SOURCE
DRAIN
2
3