m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 8

• Manufacturer Part Number: m52s128324a
• Description: 1m X 32 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
SIMPLIFIED TRUTH TABLE
Note :
Elite Semiconductor Memory Technology Inc.
Register
Refresh
Column Address
Column Address
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operating Command
Read &
Write &
1.OP Code : Operating Code
2.MRS can be issued only at all banks precharge state.
3.Auto refresh functions are as same as CBR refresh of DRAM.
4.BA0~BA1 : Bank select addresses.
5.During burst read or write with auto precharge. new read/write command can not be issued.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
Bank Active & Row Addr.
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
COMMAND
Burst Stop
Mode Register set
Auto Refresh
Self
Refresh
Bank Selection
All Banks
Auto Precharge Disable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Entry
Exit
Entry
Entry
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
L
L
L
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
X
H
H
X
X
X
X
X
H
H
X
L
L
L
CS RAS CAS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
RP
after the end of burst.
H
H
H
H
V
H
V
X
H
L
L
X
L
L
X
X
X
X
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM BA0,1 A10/AP
Publication Date: Mar. 2009
Revision: 1.4
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
M52S128324A
V
V
V
V
X
OP CODE
Row Address
H
H
H
L
L
L
X
X
X
X
X
X
X
Address
(A0~A7)
Column
Column
Address
(A0~A7)
A9~A0
A11,
8/47
X
Note
1,2
4,5
4,5
3
3
3
3
4
4
6
7