m52s128324a Elite Semiconductor Memory Technology Inc., m52s128324a Datasheet - Page 6
m52s128324a
Manufacturer Part Number
m52s128324a
Description
1m X 32 Bit X 4 Banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
1.M52S128324A.pdf
(47 pages)
- Current page: 6 of 47
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ESMT
AC OPERATING TEST CONDITIONS (V
O u t p u t
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Elite Semiconductor Memory Technology Inc.
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row active time
Row cycle time
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
RAS to CAS delay
(Fig. 1) DC Output Load Circuit
500
Ω
Parameter
Parameter
@ Operating
@ Auto Refresh
500
V
3 0 p F
DDQ
Ω
V
V
O H
O L
( D C ) = 2 . 4 V , I
( D C ) = 0 . 4 V , I
t
t
t
t
t
t
t
t
t
t
Symbol
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS
RC(min)
RFC(min)
CDL(min)
RDL(min)
BDL(min)
(max)
DD
OH
OL
= 2.5V ± 0.2V , T
= 2 mA
= -2 mA
14
18
20
42
70
70
-7
0.9XV
See Fig. 2
Version
0.5xV
0.5xV
tr/tf = 1/1
Value
100
1
2
1
DDQ
DDQ
DDQ
Output
/ 0.2
A
-10
20
30
30
50
80
80
= 0 to 70 C
(Fig. 2) AC Output Load Circuit
Z0 =50
° )
Unit
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
Publication Date: Mar. 2009
Revision: 1.4
Ω
M52S128324A
Note
Unit
1
1
1
1
1
2
2
2
ns
V
V
V
Vtt = 0.5xV
5 0
3 0 pF
Ω
DDQ
6/47
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