a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 97
![no-image](/images/no-image-200.jpg)
a3p1000-1pqg208m
Manufacturer Part Number
a3p1000-1pqg208m
Description
Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
Manufacturer
Actel Corporation
Datasheet
1.A3P1000-1PQG208M.pdf
(182 pages)
- Current page: 97 of 182
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Figure 2-27 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Enable
Preset
Data
CLK
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
B
A
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
C
D
E
DFN1E1P1
PRE
D
Q
E
Y
R e v i s i o n 0
Array
Core
Data_out
Military ProASIC3/EL Low Power Flash FPGAs
G
H
K
F
J
I
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
D
E
E
D
DFN1E1P1
DFN1E1P1
PRE
PRE
L
Q
Q
DOUT
EOUT
2- 83
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