a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 129

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Table 2-181 • A3PE3000L Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
Military-Case Conditions: T
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
J
= 125°C, VCC = 1.425 V
R e v i s i o n 0
Military ProASIC3/EL Low Power Flash FPGAs
Min.
1.61
1.60
Table 2-5 on page 2-8
1
–1
Max.
1.85
1.87
0.27
2
Min.
1.89
1.88
Std.
1
Max.
2.17
2.20
0.32
for derating
2
Units
MHz
2- 115
ns
ns
ns
ns
ns