a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 95

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

OUTBUF_LVPECL
Figure 2-26 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-147 • Minimum and Maximum DC Input and Output Levels
Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads
DC Parameter
VCCI
VOL
VOH
VIL, VIH
V
V
V
V
Input LOW (V)
1.64
*
ODIFF
OCM
ICM
IDIFF
Measuring point = V
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Supply Voltage
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
Output LOW Voltage
Output HIGH Voltage
Input LOW, Input HIGH Voltages
FPGA
trip.
See
Description
Table 2-27 on page 2-27
N
P
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
Input HIGH (V)
187 W
for a complete table of trip points.
1.94
0.625
1.762
Min.
0.96
1.01
300
R e v i s i o n 0
1.8
0
Z
Z
0
0
3.0
= 50 Ω
= 50 Ω
Max.
2.57
1.27
2.11
0.97
1.98
3.3
100 Ω
0.625
1.762
Min.
1.06
1.92
1.01
Military ProASIC3/EL Low Power Flash FPGAs
300
0
3.3
P
N
Max.
2.28
2.57
1.43
0.97
1.98
3.6
Measuring Point* (V)
FPGA
+
–
0.625
1.762
Min.
Cross point
1.30
2.13
1.01
300
0
3.6
INBUF_LVPECL
Figure
Max.
1.57
2.41
0.97
1.98
2.57
3.9
2-26. The
Units
mV
V
V
V
V
V
V
V
2- 81