a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 128
a3p1000-1pqg208m
Manufacturer Part Number
a3p1000-1pqg208m
Description
Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
Manufacturer
Actel Corporation
Datasheet
1.A3P1000-1PQG208M.pdf
(182 pages)
- Current page: 128 of 182
- Download datasheet (7Mb)
Military ProASIC3/EL DC and Switching Characteristics
2- 11 4
Table 2-179 • A3PE600L Global Resource
Table 2-180 • A3P1000 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
1.5 V DC Core Voltage
Military-Case Conditions: T
Military-Case Conditions: T
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Description
J
J
= 125°C, VCC = 1.425 V
= 125°C, VCC = 1.425 V
R e visio n 0
Min.
Min.
1.18
1.17
Table 2-6 on page 2-8
Table 2-5 on page 2-8
1
1
–1
–1
Max.
Max.
1.44
1.48
0.32
2
2
Min.
Min.
1.39
1.37
Std.
1
Std.
1
Max.
Max.
1.70
1.74
0.37
for derating
for derating
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Related parts for a3p1000-1pqg208m
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 1000K System Gates
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
A3P1000-FG144M
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FBGA 484/ProASIC3 Flash Family FPGAswith Optional Soft ARM® Support
Manufacturer:
Actel