A3P1000-FG144M Actel, A3P1000-FG144M Datasheet

A3P1000-FG144M

Manufacturer Part Number

A3P1000-FG144M

Description

A3P1000-FG144M

Manufacturer

Actel

Datasheet

1.A3P1000-1PQG208M.pdf (182 pages)

Specifications of A3P1000-FG144M

Lead_time

133

Pack_quantity

160

Comm_code

85423990

Current page: 1 of 182
Download datasheet (7Mb)

October 2008

Military ProASIC3/EL Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Military Temperature Tested and Qualified

Firm-Error Immune

Low Power

High Capacity

Reprogrammable Flash Technology

High Performance

In-System Programming (ISP) and Security

High-Performance Routing Hierarchy

Table I-1 • Military ProASIC3/EL Low-Power Devices

ProASIC3/EL Devices

ARM Cortex-M1 Devices

System Gates

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP2

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. Refer to the

2. AES is not available for ARM-enabled ProASIC3/EL devices.

• Each Device Tested from –55°C to 125°C

• Not Susceptible to Neutron-Induced Configuration Loss

• Dramatic Reduction in Dynamic and Static Power

• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

• Low Power Consumption in Flash*Freeze Mode Allows for

• Supports Single-Voltage System Operation

• Low-Impedance Switches

• 600 k to 3 M System Gates

• Up to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

† A3P1000 only supports 1.5 V core operation.

ƒ Flash*Freeze technology is not available for A3P1000.

††Pro I/Os are not available on A3P1000.

PQFP

FBGA

Instantaneous Entry To / Exit From Low-Power Flash*Freeze

Mode

Performance

PCI (1.2 V systems)

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

Cortex-M1

product brief for more information.

A3PE600L

13,824

FG484

600 k

108

Yes

270

1 k

†

Advanced and Pro (Professional) I/Os

Clock Conditioning Circuit (CCC) and PLL

SRAMs and FIFOs

ARM

• Architecture Supports Ultra-High Utilization

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay (A3PE3000L only)

• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the Military ProASIC

• Six CCC Blocks, One with Integrated PLL (ProASIC3) and All

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

• ARM Cortex™-M1 Soft Processor Available with or without

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II (A3PE3000L only)

with Integrated PLL (ProASIC3EL)

and External Feedback

systems) and 350 MHz (1.5 V systems)

and ×18 organizations available)

Operation:

– 250 MHz: For 1.2 V Systems

– 350 MHz: For 1.5 V Systems

Debug

M1A3P1000

Processor Support in ProASIC3/EL FPGAs

A3P1000

PQ208

24,576

FG144

1 M

144

Yes

154

1 k

I/O

Standards:

†

LVTTL,

M1A3PE3000L

FG484, FG896

A3PE3000L

††

75,264

3 M

504

620

112

Yes

1 k

LVCMOS

Revision 0

3EL Family

3.3 V /

†

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