agl030 Actel Corporation, agl030 Datasheet - Page 88

• Manufacturer Part Number: agl030
• Description: Igloo Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

IGLOO DC and Switching Characteristics
Table 2-138 • Output Data Register Propagation Delays
Table 2-139 • Output Data Register Propagation Delays
2 -7 4
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
1.5 V DC Core Voltage
1.2 V DC Core Voltage
J
J
= 70°C, Worst-Case V
= 70°C, Worst-Case V
A d v a n c e v 0. 3
Description
Description
CC
CC
= 1.425 V
= 1.14 V
Table 2-6 on page 2-6
Table 2-7 on page 2-7
0.00
0.00
0.24
0.00
0.24
0.19
0.31
0.28
0.00
0.00
0.24
0.00
0.24
0.19
0.31
0.28
Std.
1.00
0.51
0.70
1.34
1.34
0.00
0.19
for derating
Std.
1.52
1.15
1.11
1.96
1.96
0.00
0.19
for derating
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns