agl030 Actel Corporation, agl030 Datasheet - Page 18

no-image

agl030

Manufacturer Part Number
agl030
Description
Igloo Low-power Flash Fpgas With Flash*freeze Technology
Manufacturer
Actel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
agl030V2-CSG81
Manufacturer:
NVIDIA
Quantity:
7
Part Number:
agl030V2-CSG81
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Part Number:
agl030V2-QNG132
Manufacturer:
Actel
Quantity:
135
Part Number:
agl030V2-UCG81
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Part Number:
agl030V2-VQ100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
agl030V2-VQ100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
agl030V2-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
agl030V2-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
agl030V5-CSG81
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Part Number:
agl030V5-UCG81
Manufacturer:
NXP
Quantity:
24 680
Part Number:
agl030V5-VQ100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
agl030V5-VQG100
Manufacturer:
RN2
Quantity:
522
Part Number:
agl030V5-VQG100I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Part Number:
agl030V5-VQG100IPR09
Manufacturer:
MICROSEMI
Quantity:
6 144
IGLOO DC and Switching Characteristics
Figure 2-1 • V5 Devices – I/O State as a Function of V
2 -4
Deactivation trip point:
Activation trip point:
V
V
a
d
= 0.85 V ± 0.25 V
= 0.75 V ± 0.25 V
V
V
CC
CC
= 1.575 V
= 1.425 V
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until V
activation levels (see
When PLL power supply voltage and/or VCC levels drop below the V
0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or
the output clock is lost. Refer to the Brownout Voltage section in the
ProASIC3/E Devices
and lock recovery.
Internal Power-Up Activation Sequence
To make sure the transition from input buffers to output buffers is clean, ensure that there is no
path longer than 100 ns from input buffer to output buffer in your design.
V
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
CC
Region 1: I/O Buffers are OFF
V
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
Deactivation trip point:
Activation trip point:
CC
V
V
= V
d
a
= 0.9 V ± 0.3 V
chapter of the
= 0.8 V ± 0.3 V
Figure 2-1
CCI
+ VT
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because V
specification. For the same reason, input
buffers do not meet V
output buffers do not meet V
buffers do not meet V
meet V
and
same reason, input buffers do not
ProASIC3
below specification. For the
IH
Figure 2-2 on page 2-5
A dv a n c e v 0. 3
/V
but slower because V
IL
(except differential
(except differential inputs)
levels, and output
CCI
IH
CCI
/V
/V
I/Os are functional
I/Os are functional
CC
IL
buffers are ON.
buffers are ON.
OH
levels, and
and V
are below
Region 4: I/O
Region 4: I/O
and
OH
/V
Min V
standard; i.e., 1.425 V or 1.7 V
OL
/V
OL
levels.
voltage at a selected I/O
ProASIC3E
CC
levels.
CCI
or 2.3 V or 3.0 V
CCI
Voltage Levels
datasheet specification
is
for more details).
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, V
handbooks for information on clock
CC
is below specification.
IH
CC
/V
IL
and V
, V
CC
OH
brownout levels (0.75 V ±
/V
OL
CCPLX
Power-Up Behavior of
, etc.
exceed brownout
V
CCI

Related parts for agl030