agl030 Actel Corporation, agl030 Datasheet - Page 80

• Manufacturer Part Number: agl030
• Description: Igloo Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

IGLOO DC and Switching Characteristics
Figure 2-14 • BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation
2 -6 6
OUTBUF_LVPECL
R
T
Z
Z
Z
0
0
stub
Receiver
+
R
R
S
BLVDS/M-LVDS
Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard
to high-performance multipoint bus applications. Multidrop and multipoint bus configurations
may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the
higher drive current required by BLVDS and M-LVDS to accommodate the loading. The drivers
require series terminations for better signal quality and to control voltage swing. Termination is
also required at both ends of the bus since the driver can be located anywhere on the bus. These
configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with
appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz
with a maximum of 20 loads. A sample application is given in
buffer delays are available in the LVDS section in
page
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the
required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:
R
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It
requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It
also requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
Figure
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVDS implementation
because the output standard specifications are different.
-
S
EN
R
Z
= 60 Ω and R
S
stub
2-65.
2-15. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one
FPGA
Z
Z
Z
0
0
stub
Transceiver
+
T
R
T
= 70 Ω, given Z
S
-
N
EN
P
R
Z
S
stub
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
Z
Z
Z
0
0
stub
0
Driver
+
= 50 Ω (2") and Z
R
D
S
A d v a n c e v 0. 3
-
EN
R
Z
S
stub
187 W
Z
Z
Z
Z
Z
0
0
0
0
stub
= 50 Ω
= 50 Ω
Receiver
+
stub
R
R
Table 2-128 on page 2-65
S
-
= 50 Ω (~1.5").
EN
100 Ω
R
Z
S
stub
...
Figure
N
P
Z
Z
2-14. The input and output
0
0
FPGA
Transceiver
+
–
+
R
T
S
and
-
EN
R
INBUF_LVPECL
S
Table 2-129 on
BIBUF_LVDS
Z
Z
0
0
R
T