wm8580a Wolfson Microelectronics plc, wm8580a Datasheet - Page 48

• Manufacturer Part Number: wm8580a
• Description: Multichannel Codec With S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics plc

WM8580
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Table 39 S/PDIF Transmitter Clock Control
PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX)
The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied
externally (slave mode) or they can be generated internally by the WM8580 (master mode). Register
R9, bit 5 selects master or slave mode.
In Slave mode, the BCLK and LRCLK driving the PAIF Rx interface are the PAIFRX_BCLK and the
PAIFRX_LRCLK pins.
In master mode the BCLK and LRCLK driving the PAIF Rx are generated by the Master Mode Clock
Gen module. The control of this module is described on page 22. The clock supplied to this module
is selected by the PAIFRXMS_CLKSEL register bits. These bits select either MCLK, PLLACLK, or
PLLBCLK Unless the S/PDIF Rx interface is enabled in which case the PAIF Rx clock is forced to
use the MCLK pin since the PLLA and PLLB are not available in this mode.
Figure 29 PAIF Rx Interface Clock Configuration
Table 40 PAIF Rx Master Mode Clock Control
REGISTER
REGISTER
ADDRESS
ADDRESS
CLKSEL
PAIF 1
08h
09h
R8
R9
BIT
BIT
5:4
7:6
TX_CLKSEL
PAIFRXMS_
CLKSEL
LABEL
LABEL
DEFAULT
DEFAULT
01
00
S/PDIF Transmitter clock source
PAIF Receiver Master Mode clock
source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
DESCRIPTION
DESCRIPTION
PD, Rev 4.7, March 2009
Production Data
48