wm8580a Wolfson Microelectronics plc, wm8580a Datasheet - Page 39

• Manufacturer Part Number: wm8580a
• Description: Multichannel Codec With S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics plc

Production Data
ADC FEATURES
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ADC HIGH-PASS FILTER DISABLE
The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be
disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled.
Table 29 ADC Functions Register
ADC OVERSAMPLING RATE SELECT
The internal ADC signal processing operates at an oversampling rate of 128fs for all MCLK:LRCLK
ratios. The exception to this is for operation with a 128fs or 192fs master clock, where the internal
oversampling rate of the ADC is 64fs.
For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the
ADCOSR bit. This changes the ADC signal processing oversampling rate from 128fs to 64fs.
Similarly, for ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set
the ADCOSR bit to change the oversampling rate from 64fs to 32fs.
Table 30 ADC Functions Register
ADC MUTE
As with the DAC, each ADC channel also has a mute control bit, which mutes the inputs to the ADC.
Table 31 ADC Mute Register
REGISTER ADDRESS
REGISTER ADDRESS
ADC Control 1
ADC Control 1
ADC Control 1
REGISTER
ADDRESS
R29
1Dh
R29
1Dh
R29
1Dh
BIT
BIT
BIT
0
1
2
4
3
ADCHPD
ADCOSR
AMUTEALL
LABEL
LABEL
AMUTER
AMUTEL
LABEL
DEFAULT
DEFAULT
DEFAULT
0
0
0
0
0
ADC high-pass filter disable
ADC oversample rate select
ADC Mute select
ADC Mute select
ADC Mute select
0 = high-pass filter enabled
1 = high-pass filter disabled
0 : Normal Operation
1: mute ADC left
0 : Normal Operation
1: mute ADC right
0 : Normal Operation
1: mute both ADC channels
0 = 128/64x oversampling
1 = 64/32x oversampling
DESCRIPTION
DESCRIPTION
DESCRIPTION
PD, Rev 4.7, March 2009
WM8580
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