wm8580a Wolfson Microelectronics plc, wm8580a Datasheet - Page 45

• Manufacturer Part Number: wm8580a
• Description: Multichannel Codec With S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics plc

Production Data
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ADC INTERFACE
The ADC_CLKSEL register selects the ADC_CLK clock source from ADCMCLK, PLLACLK,
PLLBCLK, or MCLK.
If the S/PDIF receiver is enabled, PLLACLK and PLLBCLK are invalid for ADC operation, so the
choice is limited to ADCMCLK (default) or MCLK. Figure 27 illustrates this.
Figure 27 ADC Clock and ADC Rate Selection
The sample rate at which the ADC operates is determined by the ADC Rate module. Which is part of
the ADC. The ADC rate module divides down the ADC_CLK and calculates the rate at which the
ADC operates based on the ADC_CLK, the ADC_RATE and the digital routing setup. These 3 things
combine to generate the ADC_RATE_SEL. Table 36 summerises the sample rate selection based
on what sources the ADC output.
Table 36 ADC Rate Selection
The ADC_CLK clock source can be independent from the DACs and PLLs, however for
optimum performance it is recommended that clock sources on the WM8580 are
synchronous. If this condition is not met performance may be degraded.
SAIF_LRCLK (MFP7)
ADCMCLK (MFP2)
ADC Data Destination
PAIFTX =ADC
SAIFTX =ADC
S/PDIFTX =ADC
PAIFTX_LRCLK
MCLK
If the S/PDIF Rx is disabled then
ADC_CLKSEL controls the
ADC_CLK clock selection
If the S/PDIF Rx is enabled, then ADC_CLK is
forced to ADCMCLK (when ADC_CLKSEL =
00,01 or 10) or ADC_CLK is forced to MCLK pin
(when ADC_CLKSEL=11)
ADC_RATE (R29[7:5])
ADC_CLKSEL(R8[3:2])
Clock used for ADC
rate Generator (fs)
PAIFTX_LRCLK
SAIF_LRCLK
ADC_RATE
SPDIFRX_EN
Tie
Tie
11
00
PLLACLK
PLLBCLK
Comments
ADC sample rate based on PAIF Tx
Assumes that PAIF sources another
interface then ADC sample rate based on
SAIF Tx
ADC sample rate determined by the
ADC_RATE register bits R29,bits 7:5
00,01,11
11
ADC Rate
Select
0
1
ADC_CLKSEL_I
00
01
10
11
PD, Rev 4.7, March 2009
ADC_RATE_SEL
ADC_CLK
WM8580
45
ADC