wm8775 Wolfson Microelectronics plc, wm8775 Datasheet - Page 18

• Manufacturer Part Number: wm8775
• Description: 24-bit, 96khz Adc With 4 Channel I/p Multiplexer
• Manufacturer: Wolfson Microelectronics plc

WM8775
w
Figure 14 Right Justified Mode Timing Diagram
I
In I
BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is
low during the left samples and high during the right samples.
Figure 15 I
DSP MODE
In DSP/PCM mode, the left channel MSB is available on either the 1
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 16 and Figure
17. In device slave mode, Figure 18 and Figure 19, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.
2
S MODE
ADCLRC
ADCLRC
2
DOUT
BCLK
S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of
BCLK
DOUT
2
S Mode Timing Diagram
MSB
1 BCLK
1
2
MSB
1
3
LEFT CHANNEL
LEFT CHANNEL
2
3
n-2 n-1
n-2 n-1
n
LSB
n
LSB
1/fs
1/fs
MSB
1 BCLK
1
2
MSB
1
3
RIGHT CHANNEL
RIGHT CHANNEL
2
3
st
(mode B) or 2
PD, Rev 4.4, October 2008
n-2 n-1
n-2 n-1
n
LSB
Production Data
nd
n
LSB
(mode A)
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