wm8775 Wolfson Microelectronics plc, wm8775 Datasheet - Page 15

• Manufacturer Part Number: wm8775
• Description: 24-bit, 96khz Adc With 4 Channel I/p Multiplexer
• Manufacturer: Wolfson Microelectronics plc

Production Data
POWERDOWN MODES
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In Master mode BCLK and ADCLRC are generated by the WM8775. The frequency of ADCLRC is
set by setting the required ratio of MCLK to ADCLRC using the ADCRATE control bit (Table 7).
Table 7 Master Mode MCLK:ADCLRC Ratio Select
Table 8 shows the settings for ADCRATE for common sample rates and MCLK frequencies.
Table 8 Master Mode ADCLRC Frequency Selection
BCLK is also generated by the WM8775. The frequency of BCLK depends on the mode of operation.
If using 256, 384, 512 or 768fs (ADCRATE=010, 011,100 or 101) BCLK = MCLK/4. However if DSP
mode is selected as the audio interface mode then BCLK=MCLK.
The WM8775 has powerdown control bits allowing specific parts of the WM8775 to be powered off
when not being used. The 4-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN4L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs. Setting AINPD and ADCPD will powerdown everything except the references VMIDADC and
ADCREFP. These may be powered down by setting PDWN. Setting PDWN will override all other
powerdown control bits. It is recommended that the 4-channel input mux and buffer AINPD and
ADCPD are powered down before setting PDWN. The default is for all powerdown bits to be 0 i.e.
enabled.
SAMPLING
ADCRATE[2:0]
(ADCLRC)
44.1kHz
32kHz
48kHz
96kHz
RATE
010
011
100
101
ADCRATE
11.2896
12.288
24.576
8.192
256fs
=010
MCLK:ADCLRC RATIO
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
ADCRATE
16.9340
12.288
18.432
36.864
384fs
=011
Unavailable Unavailable
ADCRATE
22.5792
16.384
24.576
512fs
=100
ADCRATE
33.8688
24.576
36.864
768fs
=101
PD, Rev 4.4, October 2008
WM8775
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