wm8775 Wolfson Microelectronics plc, wm8775 Datasheet
wm8775
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wm8775 Summary of contents
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... ADC with 4 Channel I/P Multiplexer DESCRIPTION The WM8775 is a high performance, stereo audio ADC with a 4 channel input mixer. The WM8775 is ideal for digitising multiple analogue sources for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. ...
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... WM8775 DESCRIPTION ................................................................................................................1 FEATURES......................................................................................................................1 BLOCK DIAGRAM ..........................................................................................................1 PIN CONFIGURATION....................................................................................................3 ORDERING INFORMATION ...........................................................................................3 PIN DESCRIPTION .........................................................................................................4 ABSOLUTE MAXIMUM RATINGS..................................................................................5 RECOMMENDED OPERATING CONDITIONS ..............................................................5 ELECTRICAL CHARACTERISTICS ...............................................................................6 TERMINOLOGY ......................................................................................................................7 MASTER CLOCK TIMING...............................................................................................7 DIGITAL AUDIO INTERFACE – MASTER MODE ...................................................................8 DIGITAL AUDIO INTERFACE – SLAVE MODE ......................................................................9 3-WIRE MPU INTERFACE TIMING ......................................................................................10 2-WIRE MPU INTERFACE TIMING ......................................................................................10 INTERNAL POWER ON RESET CIRCUIT ...
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... AIN1R 27 AIN2L 26 AIN2R 25 AIN3L 24 AIN3R 23 AIN4L 22 AIN4R 21 AINOPL 20 AINVGL 19 AINOPR 18 AINVGR 17 AGND 16 AVDD 15 ADCREFP MOISTURE PACKAGE SENSITIVITY LEVEL 28-lead SSOP (Pb-free) 28-lead SSOP (Pb-free, tape and reel) WM8775 PEAK SOLDERING TEMPERATURE MSL2 260°C MSL2 260°C PD, Rev 4.4, October 2008 3 ...
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... WM8775 PIN DESCRIPTION PIN NAME 1 AIN1L Analogue Input 2 BCLK Digital input/output 3 MCLK Digital input 4 DOUT Digital output 5 ADCLRC Digital input/output 6 DGND 7 DVDD 8 MODE Digital Input 9 CE Digital Input 10 DI Digital input/output 11 CL Digital input 12 13 VMIDADC Analogue Output 14 ADCREFGND 15 ADCREFP Analogue Output ...
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... RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue supply range Ground AGND, DGND Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. w SYMBOL TEST CONDITIONS DVDD AVDD WM8775 MIN MAX -0.3V +3.63V -0.3V +7V DGND -0.3V DVDD + 0.3V AGND -0.3V AVDD +0.3V 37MHz -25°C +85° ...
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... WM8775 ELECTRICAL CHARACTERISTICS Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance ADC Performance Input Signal Level (0dB) SNR (Note 1,2) ...
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... MCLKL t MCLKH t MCLKY 48kHz, MCLK = 256fs unless otherwise stated. A SYMBOL TEST CONDITIONS t MCLKH t MCLKL t MCLKY After MCLK stopped After MCLK re-started WM8775 MIN TYP MAX UNIT 1000 ns 40:60 60:40 µ 0.5 1 MCLK cycle PD, Rev 4.4, October 2008 ...
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... WM8775 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK WM8775 ADCLRC ADC DOUT Figure 2 Audio Interface - Master Mode BCLK (Output) ADCLRC (Output) DOUT Figure 3 Digital Audio Data Timing – Master Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND=0V, DGND = 0V, T stated. PARAMETER SYMBOL Audio Data Input Timing Information ...
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... LRH BCLK rising edge DOUT propagation delay t DD from BCLK falling edge Table 3 Digital Audio Data Timing – Slave Mode Note: ADCLRC should be synchronous with MCLK, although the WM8775 interface is tolerant of phase variations or jitter on these signals. w DVD Controller t t BCH BCL ...
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... WM8775 3-WIRE MPU INTERFACE TIMING Figure 6 SPI Compatible Control Interface Input Timing (MODE=1) Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T PARAMETER CL rising edge to CE rising edge CL pulse cycle time CL pulse width low CL pulse width high set-up time hold time ...
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... 48kHz, MCLK = 256fs unless otherwise stated A SYMBOL MIN 600 2 t 600 3 t 600 4 t 100 600 WM8775 TYP MAX UNIT 526 kHz 300 ns 300 ns ns 900 PD, Rev 4.4, October 2008 11 ...
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... INTERNAL POWER ON RESET CIRCUIT Figure 8 Internal Power on Reset Circuit Schematic The WM8775 includes an internal Power on Reset Circuit which is used reset the digital logic into a default state after power up. Figure 8 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum threshold Vpor_off ...
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... VMID resistor string and the decoupling capacitor. The Resistor string has an typical equivalent resistance of 50kΩ (+/-20%). Assuming a 10uF capacitor, the time required for VMID to reach threshold approx 110ms. w MIN TYP 0.5 0.7 0.5 0.7 1.0 1.4 0.6 0.8 WM8775 MAX UNIT 1.0 V 1.1 V 2.0 V 1.0 V PD, Rev 4.4, October 2008 13 ...
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... If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with ADCLRC, although the WM8775 is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8775. ...
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... Table 8 Master Mode ADCLRC Frequency Selection BCLK is also generated by the WM8775. The frequency of BCLK depends on the mode of operation. If using 256, 384, 512 or 768fs (ADCRATE=010, 011,100 or 101) BCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then BCLK=MCLK. POWERDOWN MODES The WM8775 has powerdown control bits allowing specific parts of the WM8775 to be powered off when not being used ...
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... Master and Slave modes ADCDAT is always an output. The default is Slave mode. In Slave mode (MS=0) ADCLRC and BCLK are inputs to the WM8775 (Figure 11). ADCLRC is sampled by the WM8775 on the rising edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that ADCLRC is sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK ...
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... S modes, the digital audio interface outputs ADC data on DOUT modes, the minimum number of BCLKs per ADCLRC period is 2 LEFT CHANNEL n-2 n-1 MSB LSB WM8775 1/fs RIGHT CHANNEL n-2 n-1 MSB LSB PD, Rev 4.4, October 2008 17 ...
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... WM8775 ADCLRC BCLK DOUT Figure 14 Right Justified Mode Timing Diagram MODE mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is low during the left samples and high during the right samples. ...
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... Production Data Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 18 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) w WM8775 PD, Rev 4.4, October 2008 19 ...
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... WM8775 Figure 19 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) CONTROL INTERFACE OPERATION The WM8775 is controlled using a 3-wire serial interface in a SPI compatible configuration or a 2-wire serial interface mode. The interface type is selected by the MODE pin as shown in Table 9. MODE 0 1 Table 9 Control Interface Selection via MODE pin ...
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... DI (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8775 and the R/W bit is ‘0’, indicating a write, then the WM8775 responds by pulling DI low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8775 returns to the idle condition and wait for a new start condition and valid address ...
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... REGISTER ADDRESS Interface Control ADC MASTER MODE Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and BCLK are outputs and are generated by the WM8775. In Slave mode ADCLRC and BCLK are inputs to WM8775. REGISTER ADDRESS Interface Control ...
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... Production Data MASTER MODE ADCLRC FREQUENCY SELECT In Master mode the WM8775 generates ADCLRC and BCLK. These clocks are derived from the master clock. The ratio of MCLK to ADCLRC is set by ADCRATE. REGISTER ADDRESS ADCLRC Frequency ADC OVERSAMPLING RATE SELECT For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs ...
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... WM8775 ADC GAIN CONTROL The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right. The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows further attenuation (after the ADC) from -21 ...
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... Mute for left channel ADC 0: Normal Operation 1: Mute ADC left 0 Mute for right channel ADC 0: Normal operation 1: Mute ADC right BIT LABEL R11(0Bh) 8 ADCHPD 0001011 DESCRIPTION DEFAULT DESCRIPTION 0 ADC High pass filter disable: 0: High pass filter enabled 1: High pass filter disabled PD, Rev 4.4, October 2008 WM8775 25 ...
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... WM8775 LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8775 has an automatic pga gain control circuit, which can function as a peak limiter automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the ADC ...
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... DEFAULT 3:0 LCT[3:0] 1011 (-5dB steps. For the ALC this gives times from n ) steps, from 8.4ms, 16.8ms, 33.6ms etc. to WM8775 DESCRIPTION Enable the PGA gain control circuit Disabled 1 = Enabled LC function select 00 = Limiter 01 = ALC Right channel only 10 = ALC Left channel only 11 = ALC Stereo ...
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... WM8775 REGISTER ADDRESS R18(12h) 0010010 ALC Control 3 TRANSIENT WINDOW (LIMITER ONLY) To prevent the limiter responding to to short duration high ampitude signals (such as hand-claps in a live performance), the limiter has a programmable transient window preventing it responding to signals above the threshold until their duration exceeds the window period. The Transient window is set in register TRANWIN ...
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... When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8775 has a noise gate function that prevents noise pumping by comparing the signal level at the AINL1/2/3/4 and/or AINR1/2/3/4 pins against a noise gate threshold, NGTH. The noise gate cuts in when: • ...
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... WM8775 When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping would normally when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. ...
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... Writing to register 0010111 will cause a register reset, resetting all register bits to their default values. REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8775 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B B ...
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... WM8775 REGISTER BIT LABEL ADDRESS R7 (07h) 3 TOD 0000111 Timeout Clock Disable R11 (0Bh) 1:0 ADCFMT[1:0] 0001011 Interface Control 2 ADCLRP 3 ADCBCP 5:4 ADCWL[1:0] 6 ADCMCLK 8 ADCHPD 12 (0Ch) 2:0 ADCRATE[2:0] 0001100 Master Mode Control 3 ADCOSR 8 ADCMS R13 (0Dh) 0 PWDN 0001101 Powerdown Control 1 ADCPD 6 AINPD w DEFAULT 0 ADC Analogue PGA Zero cross detect timeout disable ...
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... ALC mode 9.6ms) 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms ….(time doubles for every step) 1010 or higher: 34.3ms WM8775 Limiter Mode 0000: 250us 0001: 500us… 0010: 1ms (time doubles with every step) 1010 or higher: 256ms Limiter mode 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms … ...
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... WM8775 R19 (13h) 0 NGAT 0010011 Noise Gate Control 4:2 NGTH R20 (14h) 3:0 MAXATTEN [3:0] 0010100 Limiter Control 6:4 TRANWIN [2:0] R21 (15h) 3:0 AMX[3:0] 0010101 ADC Mixer Control 6 MUTERA 7 MUTELA 8 LRBOTH R23 (17h) [8:0] RESET 0010111 Software Reset Table 13 Register Map Description w 0 Noise gate enable (ALC only) ...
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... Table 14 Digital Filter Characteristics ADC FILTER RESPONSES 0 -20 -40 -60 -80 0 0.5 1 1.5 Frequency (Fs) Figure 25 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER The WM8775 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial H( 0.9995z 0 -5 -10 -15 0 0.0005 0.001 ...
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... WM8775 APPLICATIONS INFORMATION EXTERNAL CIRCUIT CONFIGURATION In order to allow the use of 2V rms and larger inputs to the ADC inputs, a structure is used that uses external resistors to drop these larger voltages. This also increases the robustness of the circuit to external abuse such as ESD pulse. Figure 28 shows the ADC input multiplexor circuit with external components allowing 2Vrms inputs to be applied ...
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... Production Data RECOMMENDED EXTERNAL COMPONENTS Figure 29 Recommended External Component Diagram w WM8775 PD, Rev 4.4, October 2008 37 ...
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... WM8775 PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c 0.09 D 9.90 10.20 e 0.65 BSC E 7.40 7.80 E 5.00 5. 0.55 0.75 L 1.25 REF 1 θ JEDEC.95, MO-150 REF: NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. ...
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... Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w WM8775 PD, Rev 4.4, October 2008 39 ...