spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet - Page 35

• Manufacturer Part Number: spear-09-h022
• Description: Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
• Manufacturer: STMicroelectronics

SPEAR-09-H022
9.2
Reset and PLL change parameters sequence
Figure 4
The system remains in an IDLE state until RESET signal is asserted: RESET
When RESET = 0 the FSM change state and reaches the PLL PWR-UP state; when PLL
locks (PLL_LOCK = 1), means that the PLL_OUT signal oscillates at 264 MHz and the PLL
starts to work, so that the FSM advances in the next states.
In CLOCK ENABLED state the clocks can propagate in the system; then the FSM goes in
SYSTEM ON state; it remains in this state in the normal chip working.
Figure 4.
To reach at a clock frequency of 266 MHz, PLL had to be appropriately programmed
because this frequency isn't an integer multiple of 12 MHz.
After this programming, the FSM stops all the clocks and exits from SYSTEM ON state
proceeding in PLL SETTING state; here the new parameters are stored in the PLL.
If the PLL isn't in Dithered mode the FSM waits for PLL lock, going in LOCK WAIT state, and
then will reach SYSTEM ON state when PLL locks.
If the PLL is in Dithered mode, the lock signal loses his meaning and there's no need to wait
for PLL lock, so the FSM jumps directly from PLL SETTING to SYSTEM ON.
When FSM is in SYSTEM ON, all clocks are enabled.
shows a simplified flow chart of clock system FSM.
State machine of clock system
Clock and reset system
→
0.
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