spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet - Page 30

• Manufacturer Part Number: spear-09-h022
• Description: Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
• Manufacturer: STMicroelectronics

Power on sequence
7
7.1
7.1.1
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Power on sequence
SPEAr Head200 software architecture
Boot process
Memory mapping
A major consideration in the design of an embedded ARM application is the layout of the
memory map, in particular the memory that is situated at address 0x0. Following reset, the
core starts to fetch instructions from 0x0, so there must be some executable code
accessible from that address. In an embedded system, this requires ROM to be present, at
least initially.
Serial Flash at 0x0
The SPEAr Head200 has been designed to use the REMAP concept into its AHB primary
bus decoder. The decoder selection for the initial address range (first 64 MB) is conditioned
with the content of an AHB remap register, which can be programmed by software at any
time.
The Serial Flash memory space is accessible in the address range 0x9600_0000 -
0x99FF_FFFF (64 MB), with or without remap.
At reset, the Serial Flash memory is 'aliased' at 0x0, which means that the AHB decoder
selects the Serial Flash space when accessing the address range 0x0000_0000 to
0x03FF_FFFF. Please note that DRAM is unreachable in this state.
Table 4.
DRAM at 0x0
After reset, the boot program makes the remapping, so that the system will be able to
access the complete 256 MB of logic memory space associated to DRAM in the range
0x0000_0000 - 0x0FFF_FFFF.
Table 5.
0x9600_0000 - 0x99FF_FFFF
0x0000_0000 - 0x03FF_FFFF
0x9600_0000 - 0x99FF_FFFF
0x0000_0000 - 0x0FFF_FFFF
ADDRESS RANGE
ADDRESS RANGE
Memory mapping at reset (REMAP = 0)
Memory Mapping after reset after remapping
SIZE [MB]
SIZE [MB]
256
64
64
64
Serial Flash (remap)
DESCRIPTION
DESCRIPTION
Serial Flash
Serial Flash
DRAM
SPEAR-09-H022