xr17v258 Exar Corporation, xr17v258 Datasheet - Page 9

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
The XR17V258 UART has three different sets of registers as shown in
Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to the
PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI
local bus specification. The second register set is the Device Configuration Registers that are also
accessible directly from the PCI bus for programming general operating conditions of the device and
monitoring the status of various functions common to all eight channels. These functions include all 8 channel
UARTs’ interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/
outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each
UART channel has its own set of internal UART Configuration Registers for its own operation control and
status reporting. All 8 sets of channel registers are embedded inside the device configuration registers space,
which provides faster access. The second and third set of registers are mapped into 4K of the PCI bus memory
address space. The following paragraphs describe all 3 sets of registers in detail.
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, located at an address offset of
0x10 in the configuration space. Custom modification of certain registers is possible by using an external
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of
information (see
F
1.0 XR17V258 INTERNAL REGISTERS
1.1
IGURE
D evic e
R eg is ter s ar e mapped on
byte
U AR T [7:0]
R eg is ter ( BAR ) in a 4K-
to the Bas e Addr es s
PC I Loc al Bus
3. T
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
Inter fac e
of
C onfig ur ation
memor y addr es s
HE
s pac e
C onfig ur ation
XR17V258 R
“Section 1.4, EEPROM Interface” on page
and
EGISTER
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
S
ETS
C onfig ur ation
R eg is ter s for Plug -
and- Play
PC I Loc al Bus
C onfig ur ation
T IM ER , R EG
C hannel 2
C hannel 3
C hannel 4
C hannel 5
C hannel 6
C hannel 7
C hannel 0
C hannel 0
C hannel 1
IN T , M PIO ,
Auto
9
Spac e
14) required by the auto-configuration setup.
0 x 0 0 0 0
0 x 0 0 8 0
0 x 0 2 0 0
0 x 0 4 0 0
0 x 0 6 0 0
0 x 0 8 0 0
0 x 0 A 0 0
0x0C 00
0x0E00
0x0F F F
Vendor
and Pr oduc t M odel N umber
in Exter nal EEPR O M
D evic e
16550 C ompatible and EXAR
Figure
Sleep, R es et, D VID , D R EV
and Sub- vendor
U AR T [7:0]
16- bit
8
Enhanc ed
M ultipur pos e
C onfig ur ation
c hannel
3. The PCI Local Bus
R eg is ter s
T imer /C ounter ,
C onfig ur ation
Inter r upts ,
R eg is ter s
ID
I/O s ,
R eg is ter s
P CI RE G S -1
XR17V258