xr17v258 Exar Corporation, xr17v258 Datasheet - Page 45

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
ISR[0]: Interrupt Status
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This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR bits [5:4] are associated with these 2 bits. These 2 bits are used to set the trigger level for the
receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses
the trigger level.
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
The FCTR bits [7:6] are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software compatibility.
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FCR[2]: TX FIFO Reset
This bit is only active when FCR bit [0] is active.
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FCR[1]: RX FIFO Reset
This bit is only active when FCR bit [0] is active.
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FCR[0]: TX and RX FIFO Enable
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5.6
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
Logic 0 = Set DMA to mode 0 (default).
Logic 1 = Set DMA to mode 1.
Logic 0= No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FIFO Control Register (FCR) - Write Only
Table 16
shows the complete selections. Note that the receiver and the transmitter cannot use
Table 16
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
below shows the selections.
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XR17V258