xr17v258 Exar Corporation, xr17v258 Datasheet - Page 39

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
A
N
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit [0]. TSR shifts out every data bit with the 16X or 8X
internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of
data bits, inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are
reported in the Line Status Register (LSR bit [6:5]).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (bit [0]) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit[0]. A THR empty
interrupt can be generated when it is enabled in IER bit [1].
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit [5]) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit [1]) when it is
enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes completely empty.
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
4.6
T
A3-A0
4.6.1
4.6.2
DDRESS
OTE
ABLE
:
compatibility during Internal loopback, see
MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V258. They are present for 16C550
14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
Transmitter
RXCNT
RXTRG
XCHAR
TXCNT
TXTRG
XOFF1
XOFF2
XON1
XON2
N
Transmit Holding Register (THR)
Transmitter Operation in non-FIFO Mode
EFR
R
AME
EG
R
W
R/W
EAD
W
W
W
W
W
W
RITE
R
R
R
/
Enable
B
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
CTS/
Auto
DSR
IT
0
[7]
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
Enable
B
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
RTS/
Auto
DTR
IT
0
[6]
Special
B
Select
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Char
IT
Figure 14
0
[5]
MCR[7:5],
MCR[3:2],
FCR[5:4],
IER [7:5],
ISR [5:4],
MSR[7:2]
39
Enable
B
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
.
IT
0
[4]
Indicator
TX Xon
B
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
ware
Flow
Soft-
Cntl
IT
[3]
Indicator
TX Xoff
B
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
[2]
S
HADED BITS ARE ENABLED BY
Xon Det.
Indicator
B
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Bit [1]
Soft-
ware
Flow
Cntl
IT
[1]
Xoff Det.
Indicator
B
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Bit [0]
Soft-
ware
Flow
Cntl
IT
[0]
XR17V258
after read
EFR B
Self clear
C
OMMENT
IT
-4.