xr17v258 Exar Corporation, xr17v258 Datasheet - Page 3

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
PIN DESCRIPTIONS
PCI LOCAL BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
AD31-AD25,
AD23-AD16,
AD15-AD8,
DEVSEL#
AD7-AD0
FRAME#
C/BE0#-
C/BE3#
TRDY#
STOP#
PERR#
SERR#
RTS0#
CTS0#
IRDY#
IDSEL
AD24,
INTA#
PME#
N
RST#
CLK
PAR
RX0
TX0
AME
36,25,14,2
138-144,
26-33,
37-44
P
6-13,
134
135
133
125
132
127
131
111
15
16
17
21
18
24
22
23
IN
1,
3
#
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
T
OD
OD
OD
YPE
IO
IO
O
O
O
O
O
O
I
I
I
I
I
I
I
I
PCI bus reset input (active LOW). It resets the PCI local bus configuration
space registers, device configuration registers and UART channel registers to
the default condition.
PCI bus clock input of up to 66.67MHz.
Address data lines [31:0] (bidirectional).
Bus transaction cycle frame (active LOW). It indicates the beginning and
duration of an access.
Bus command/byte enable [3:0] (active LOW). This line is multiplexed for bus
command during the address phase and byte enables during the data phase.
Initiator ready (active LOW). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
Target ready (active LOW).
Target request to stop current transaction (active LOW).
Initialization device select (active HIGH).
Device select to the XR17V258 (active LOW).
Device interrupt from XR17V258 (open drain, active LOW).
Power Management Event signal. While in D3
in the Power Management Control/Status Register is set, the V258 asserts
the PME# upon receiving a new character or upon change of state of modem
inputs on any channel.
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active HIGH).
Data parity error indicator, except for special cycle transactions (active LOW).
Optional in bus target application.
System error indicator, Address parity or data parity during special cycle
transactions (open drain, active LOW). Optional in bus target application.
UART channel 0 Transmit Data or infrared transmit data.
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted internally prior to
decoding by setting FCTR bit [4].
UART channel 0 Request to Send or general purpose output (active LOW).
UART channel 0 Clear to Send or general purpose input (active LOW).
3
D
ESCRIPTION
hot
state, if the PME_Enable bit
XR17V258