xr17v258 Exar Corporation, xr17v258 Datasheet - Page 18

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
The XR17V258 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is an 8-bit indicator representing all 8 channels with each bit
representing each channel from 0 to 7. This permits the interrupt service routine to quickly determine which
UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines.
INT0 bit [0] represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or
modem port status requires service. Other bits in the INT0 register provide indication for the other channels
with bit [7] representing UART channel 7 respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for all 8 channels. bits [10:8] representing channel 0 and bits [31:29] representing channel 7
respectively. All 8 channel interrupts status are available with a single DWORD read operation. This feature
allows the host another method to quickly service the interrupts, thus reducing the service interval and host
bandwidth requirement.
All bits start up zero. A special interrupt condition is generated by the V258 upon awakening from sleep after all
eight channels were put to sleep mode earlier.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and
bit [7] indicates channel 7. Logic 1 indicates the channel N [7:0] has called for service. The interrupt bit clears
after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section.
INT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded
into 3 bits for receive, transmit, and status. bits [10:8] represent channel 0 and go up to channel 7 with
bits [31:29]. The 3-bit encoding and their priority order are shown below in
interrupts are for the device and therefore they exist within channel 0 space and not in other channel interrupt.
1.6.1
0x088-08B
0x08C-08F
0x080
0x084-087
0x090-093
A
DDRESS
-
083
The Global Interrupt Register
GLOBAL INTERRUPT REGISTER (DWORD)
T
ANCILLARY1 (read/write)
ABLE
ANCILLARY2 (read-only)
INTERRUPT (read-only)
INT3 [31:24]
TIMER (read/write)
MPIO (read/write)
7: D
R
EGISTER
The INT0 register provides individual status for each channel
EVICE
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7
C
ONFIGURATION
Individual UART Channel Interrupt Status
Ch-6
INT2 [23:16]
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
B
TIMERMSB
Figure 5
YTE
MPIOSEL
MPIOINT
INT0 Register
SLEEP
INT3
3 [31:24]
R
EGISTERS SHOWN IN
18
shows the 4-byte interrupt register and its make up.
INT1 [15:8]
B
YTE
TIMERLSB
MPIOINV
RESET
REGB
INT2
2 [23:16]
[default 0x00-00-00-00]
DWORD
TIMER (reserved)
Table 8
INT0 [7:0]
B
YTE
MPIO3T
ALIGNMENT
REGA
DVID
INT1
1 [15:8]
. The Timer and MPIO
xr
B
TIMERCNTL
YTE
8XMODE
MPIOLVL
DREV
INT0
REV. 1.0.0
0 [7:0]