xr17v258 Exar Corporation, xr17v258 Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
xr17v258
Manufacturer Part Number
xr17v258
Description
66mhz Pci Bus Octal Uart With Power Management Support
Manufacturer
Exar Corporation
Datasheet
1.XR17V258.pdf
(70 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr17v258IV-F
Manufacturer:
EXAR
Quantity:
295
Company:
Part Number:
xr17v258IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xr17v258IV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
xr17v258IVTR-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
A
O
0x18h
DDRESS
0x0C
0x1C
0x00
0x04
0x08
0x10
0x14
0x20
FFSET
31:16
15:0
31
30
29:28
27
26:25
24
23
22
21
20
19:16
15:9,7,
5,4,3,2
8
6
1
0
31:8
7:0
31:24
23:16
15:8
7:0
31:12
11:0
31:0
31:0
31:0
31:0
B
ITS
RWC
RWC
RWR
RWR
RWR
RWR
EWR
EWR
EWR
T
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1: PCI L
Device ID (Exar device ID number)
Vendor ID (Exar) specified by PCISIG
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
Target Abort.
DEVSEL# timing.
Unemployments bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bit
66MHz capable
Capabilities List
Reserved Status bits
Command bits (reserved)
SERR# driver enable. logic 1=enable driver and 0=disable driver
Parity error enable. logic 1=respond to parity error and 0=ignore
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
Device’s response to I/O space accesses is disabled.
(0 = disable I/O space accesses)
Class Code (Default is ’Simple 550 Communication Controller’)
Revision ID (Exar device revision number)
BIST (Built-in Self Test)
Header Type (a single function device with one BAR)
Unimplemented Latency Timer (needed only for bus master)
Unimplemented Cache Line Size
Memory Base Address Register (BAR)
Claims a 4K address space for the memory mapped UARTs
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
OCAL
B
US
C
ONFIGURATION
10
D
ESCRIPTION
S
PACE
R
EGISTERS
Current Rev. value
xr
(
HEX OR BINARY
R
0x00000000
0x00000000
0x00000000
0x00000000
ESET
0x070002
0x13A8
0x0258
0x0000
0000b
0x000
0x00
0x00
0x00
0x00
0x00
00b
00b
0b
0b
0b
0b
1b
0b
1b
1b
0b
0b
0b
0b
REV. 1.0.0
V
ALUE
)