xr16v794iv Exar Corporation, xr16v794iv Datasheet - Page 53

• Manufacturer Part Number: xr16v794iv
• Description: High Performance 2.25v To 3.6v Quad Uart With Fractional
• Manufacturer: Exar Corporation

REV. 1.0.0
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 28
ABSOLUTE MAXIMUM RATINGS ................................................................................. 43
ELECTRICAL CHARACTERISTICS............................................................................... 43
TABLE OF CONTENTS .....................................................................................................
DC E
AC E
R
TIMER OPERATION ................................................................................................................................................ 23
3.2 UART CHANNEL CONFIGURATION REGISTERS.......................................................................................... 26
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 28
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ............................................................................... 28
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY .................................................................................. 30
4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 31
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 32
4.7 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 34
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 35
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 36
4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY.................................................................................... 37
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 38
4.12 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................... 38
4.13 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 39
4.14 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 41
4.15 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 41
4.16 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 41
4.17 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY .................................................................. 41
4.18 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 41
4.19 XCHAR REGISTER, READ ONLY .................................................................................................................. 41
EVISION
T
F
F
T
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
ABLE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
LECTRICAL
LECTRICAL
3.1.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 24
3.1.4 REGA [7:0](DEFAULT 0X00) ....................................................................................................................................... 24
3.1.5 RESET [7:0] (DEFAULT 0X00)..................................................................................................................................... 24
3.1.6 SLEEP [7:0] ...................................................................................................................................... (DEFAULT 0X00) 24
3.1.7 DEVICE IDENTIFICATION AND REVISION................................................................................................................. 24
3.1.8 REGB [7:0] ....................................................................................................................................... (DEFAULT 0X00) 25
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 28
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 30
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 30
10: TIMER C
11: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 26
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
13: I
14: T
15: P
16: A
17: 16 S
18: S
19: UART RESET CONDITIONS ...................................................................................................................................... 42
14. T
15. I
16. 16 M
17. 68 M
18. M
19. R
20. T
21. R
22. T
H
3.1.2.2 TIMER [7:0] R
3.1.2.3 TIMERCNTL [7:0] R
3.1.7.1 DVID [7:0] (
3.1.7.2 DREV [7:0] (
ISTORY
NTERRUPT
RANSMIT AND
ARITY
UTO
OFTWARE
NTERRUPT
IMER
RANSMIT
RANSMIT
ECEIVE
ECEIVE
ODEM
ELECTABLE
C
C
RS485 H
ODE
ODE
/C
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
HARACTERISTICS
P
HARACTERISTICS
..................................................................................................................................... 51
ROGRAMMING
I
ONTROL
OUNTER CIRCUIT
NPUT
I
I
(I
(M
NTERRUPT
NTERRUPT
S
F
I
I
NTERRUPT
NTERRUPT
NTEL
O
OURCE AND
LOW
OTOROLA
UTPUT IN
R
/O
ALF
H
ECEIVE
) D
UTPUT
YSTERESIS
C
C
DEFAULT
DEFAULT
-
OMMANDS
ONTROL
DUPLEX
ATA
ESERVED
T
T
) D
T
T
IMING
IMING
O
................................................................................................................................................. 33
FIFO T
T
IMING
IMING
B
P
............................................................................................................................................. 23
NE
IMING
ATA
US
RIORITY
EGISTER
0
D
F
-S
............................................................................................................. 43
............................................................................................................. 44
(0
X
L
[N
[FIFO M
UNCTIONS
R
....................................................................................................................................... 22
IRECTION
48) ................................................................................................................................. 25
....................................................................................................................................... 22
X
EVELS
B
HOT AND
[N
[FIFO M
EAD AND
01) .............................................................................................................................. 25
RIGGER
.................................................................................................................................... 48
ON
US
ON
-FIFO M
L
R
.............................................................................................................................. 22
-FIFO M
EVEL
EAD AND
W
ODE
C
HEN
ODE
R
T
........................................................................................................................ 40
W
ONTROL
ABLE AND
E
]................................................................................................................... 49
..................................................................................................................... 30
RITE
-
ODE
]................................................................................................................. 49
TRIGGERABLE
T
ODE
RIGGER
W
]........................................................................................................... 48
T
RITE
]......................................................................................................... 49
IMING
D
L
ELAY FROM
II
EVEL
T
T
................................................................................................. 46
IMING
ABLE
M
S
ODES
ELECTION
-D
........................................................................................ 47
T
IS
RANSMIT
................................................................................. 23
S
ELECTED
.......................................................................... 32
HADED BITS ARE ENABLED BY
-
TO
-R
................................................................ 39
ECEIVE
................................................. 37
EFR B
XR16V794
IT
-4. ....... 27
I