xr16v794iv Exar Corporation, xr16v794iv Datasheet - Page 38

• Manufacturer Part Number: xr16v794iv
• Description: High Performance 2.25v To 3.6v Quad Uart With Fractional
• Manufacturer: Exar Corporation

XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
MSR [3]: Transmitter Disable
This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set
to a ’1’, the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will stay in
the FIFO and will not be sent out. When this bit is set to a ’0’, the bytes currently in the TX FIFO will be sent
out. Please note that setting this bit to a ’1’ stops any character from going out. Also, this bit must be a ’0’ for
Send Char Immediate function (see MCR[3]).
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MSR [2]: Receiver Disable
This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to
a ’1’, the receiver will not receive any more characters until it is enabled again by setting this bit to a ’0’. Data
currently in the RX FIFO can be read out. Please note that setting this bit to a ’1’ prevents any character from
coming in.
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MSR [1:0]: Reserved
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See in
FCTR bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR#
output will de-assert at 60 and re-assert at 16.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
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FCTR[4]: Infrared RX Input Logic Select
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FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is
selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger
level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control.
Table 17
4.11
4.12
Logic 0 = Enable Transmitter (default).
Logic 1 = Disable Transmitter.
Logic 0 = Enable Receiver (default).
Logic 1 = Disable Receiver.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to
LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from
LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
SCRATCH PAD REGISTER (SPR) - Read/Write
FEATURE CONTROL REGISTER (FCTR) - Read/Write
shows the 16 selectable hysteresis levels.
38
Table 14
for complete selection with FCR bit 4-5 and
REV. 1.0.0