xr16v794iv Exar Corporation, xr16v794iv Datasheet - Page 28

• Manufacturer Part Number: xr16v794iv
• Description: High Performance 2.25v To 3.6v Quad Uart With Fractional
• Manufacturer: Exar Corporation

XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
N
ibility during Internal loopback, see
SEE ”RECEIVER” ON PAGE 11. .
SEE ”TRANSMITTER” ON PAGE 9. .
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the
RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 3:0 enables the XR16V794 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used
in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO mode).
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
T
4.3.1
4.3.2
A
OTE
ABLE
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
A3-A0
DDRESS
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR16V794. They are present for 16C550 compat-
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
Receive Holding Register (RHR) - Read Only
Transmit Holding Register (THR) - Write Only
Interrupt Enable Register (IER) - Read/Write
IER versus Receive FIFO Interrupt Mode Operation
IER versus Receive/Transmit FIFO Polled Mode Operation
RXTRG
XCHAR
TXTRG
RXCNT
XOFF1
XOFF2
XON1
XON2
N
R
AME
EG
W
R
EAD
RITE
W
W
W
W
W
W
R
R
/
B
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
-7
Figure 11
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
IT
0
-6
.
B
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
-5
28
B
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
-4
Indicator
TX Xon
B
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
IT
-3
Indicator
TX Xoff
B
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
IT
-2
S
HADED BITS ARE ENABLED BY
Xon Det.
Indicator
B
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
IT
-1
Xoff Det.
Indicator
B
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
IT
-0
REV. 1.0.0
EFR B
C
after read
Self clear
OMMENT
IT
-4.