73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 85

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

STXCtl, b7 “I2CMODE”, and the definition of
When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card
interface operates in synchronous mode and there are changes in the definition and behavior of pertinent
register bits and associated circuitry. The following requirements are to be noted:
1. The source for the smart card clock (CLK or SCLK) is the ETU counter. Only the actively selected
2. The control bits CLKLVL, SCLKLVL, CLKOFF, and SCLKOFF are functional in synchronous mode.
3. The Rlen(7:0) is configured to count the falling edges of the ETU clock (CLK or SCLK) after it has
4. The FIFO is not clocked by the first CLK (falling) edge resulting from a CLKOFF de-assertion (a clock
5. The state of the pin IO or SIO is sampled on the rising edge of CLK/SCLK and stored in bit 5 of the
6. When Rlen = max or 0 and I2CMODE = 1 (STXCtl, b7), the IO or SIO signal is directly controlled by
7. In the
8. Care must be taken to clear the RX and TX FIFOs at the start of any transaction. The user shall read
Special bits that are only active for sync mode include: SRXCtl, b7 “BIT9DAT”,
interrupt, and
Rev. 1.2
interface can have a running synchronous clock. In contrast, an unselected interface may have a
running clock in the asynchronous mode of operation.
When the CLKOFF bit is set, it will not truncate either the logic low or logic high period when the (stop
at) level is of opposite polarity. The CLK/SCLK signal will complete a correct logic low or logic high
duty cycle before stopping at the selected level. The CLK “start” is a result of the falling edge of the
CLKOFF bit. Setting clock to run when it is stopped low will result in a half period of low before going
high. Setting clock to run when it is stopped high will result in the clock going low immediately and
then running at the selected rate with 50% duty cycle (within the limitations of the ETU divisor value).
been loaded with a value from 1 to 255. A value of 0 disables the counting function and RLen
functions such as I/O source selection (I/O signal bypasses the FIFOs and is controlled by the
SCCLK/SCECLK
WAITTO interrupt (SCInt, bit 7), which is maskable via WTOIEN (SCIE, bit 7).
reloaded in order to start the counting/clocking process again. This allows the processor to select the
number of CLK cycles and hence, the number of bits to be read or written to/from the card.
start event) when the CLK was stopped in the high state and RLen has been loaded but not yet
clocked.
SCCtl/SCECtl
the data and direction bits in the respective
TX FIFO is bypassed.
nine-bit words with the state of the ninth bit being readable in SRXCtl, bit 7 (B9DAT). The RXDAV
interrupt will occur when the ninth bit has been clocked in (rising edge of CLK or SCLK).
the RX FIFO until it indicates empty status. Reading the TX FIFO twice will reset the input byte
pointer and the next write to the TX FIFO will load the byte to the “first out” position. Note that the bit
pointer (serializer/deserializer) is reset to bit 0 on any change of the TX/RXD bit.
SPrtcol
SCIE
register, bit 6 (MODE9/8B) becomes active. When set, the RXData FIFO will read
register.
b7, which was “WTOIEN”, becomes RLenIEN.
SFRs). When the RLen counter reaches the “max” (loaded) value, it sets the
SCInt
SCCtl
b7, which was “WAITTO”, becomes RLenINT
and
SCECtl
register. The state of the data in the
SPrtcol
I2CMODE
b6 “MODE9/8B”,
It must be
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