73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 60

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

or write 1 or 2 bytes of data per data transfer frame. The MPU communicates with the interface through
six dedicated SFR registers:
•
•
•
The
automatically de-asserted when a subsequent I
1.7.13 I
The 73S1217F includes a dedicated fast mode, 400kHz I
•
•
•
operation. The
the I
clock from the time-base circuits.
1.7.13.1
To write data on the I
following sequence:
1. Write slave device address to Device Address register (DAR). The data contains 7 bits for the slave
2. Write data to Write Data register (WDR). This data will be transferred to the slave device.
3. If writing 2 bytes, set bit 0 of the Control and Status register (CSR) and load the second data byte to
4. Set bit 1 of the
5. Wait for I
60
Device Address (DAR)
Write Data (WDR)
Secondary Write Data (SWDR)
Read Data (RDR)
Secondary Read Data (SRDR)
Control and Status (CSR)
device address and 1 bit of op-code. The op-code bit should be written with a ‘0’ to indicate a write
operation.
Secondary Write Data register (SWDR).
information about the INT6Ctl,
2
DAR
C transaction is complete, the I
2
register is used to set up the slave address and specify if the transaction is a read or write
C Master Interface
I
2
C Write Sequence
2
C interrupt to be asserted. It indicates that the write on I
CSR
CSR
register sets up, starts the transaction and reports any errors that may occur. When
2
C Master Bus, the 80515 has to program the following registers according to the
register to start I
IEN1
2
C interrupt is reported via external interrupt 6. The I
and
2
C Master Bus.
IRCON
2
C transaction is started. The I
register for masking and flag operation.
2
C Master interface. The I
2
C Master Bus is done. Refer to
2
C interface uses a 400kHz
2
C interface can read
2
C interrupt is
Rev. 1.2