73s1217f68im Maxim Integrated Products, Inc., 73s1217f68im Datasheet - Page 84

• Manufacturer Part Number: 73s1217f68im
• Description: Bus-powered 80515 System-on-chip With Usb, Iso 7816 / Emv, Pinpad And More
• Manufacturer: Maxim Integrated Products, Inc.

1.7.17.4
It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart
cards. This is called Bypass mode. In this mode the embedded firmware will communicate directly with
the selected smart card and drive I/O during transmit and read I/O during receive in order to communicate
with the smart card. In this mode, ATR processing is under firmware control. The firmware must
sequence the interface signals as required. Firmware must perform TS processing, parity checking,
break generation and CRC/LRC calculation (if required).
1.7.17.5
The 73S1217F supports synchronous operation. When sync mode is selected for either interface, the
CLK signal is generated by the ETU counter. The values in FDReg, SCCLK, and
obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the
interface must be selected to obtain a smart card clock signal. In sync mode, input data is sampled on
the rise of CLK, and output data is changed on the fall of CLK.
Special Notes Regarding Synchronous Mode Operation
84
T = 1 Mode
ATR Timing Parameters
TRANSMISSION
BLOCK1
Bypass Mode
Synchronous Operation Mode
T = 0 Mode
IO
RLen(7:0)
RST
VCC_OK
CHAR 1
EGT
CHAR 1
Figure 21: Guard, Block, Wait and ATR Time Definitions
(By seting Last_TXByte and
TX/RXB=0 during CHAR N,
RX mode will start after last
TSTO(7:0)
CHAR 2
< WWT
> EGT
WWT is set by the value in the BWT registers.
TX byte)
CHAR N
IWT(15:0)
CHAR 1
> BWT
CHAR 2
ATRTO(15:0)
CHAR
CHAR 2
N+1
< CWT
RECEPTION
BLOCK2
CHAR
N+2
CHAR N
CHAR
N+3
SCECLK
BGT(4:0)
must be set to
TX
Rev. 1.2