km416s1120d ETC-unknow, km416s1120d Datasheet - Page 7

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

(AC operating conditions unless otherwise noted)
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
Number of valid output data
KM416S1120D
AC OPERATING TEST CONDITIONS
Note :
OPERATING AC PARAMETER
Notes :
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The DC/AC Test Output Load of KM416S1120D-C/6/7 is 30pF.
2. The VDD condition of KM416S1120D-C/6 is 3.135V~3.6V.
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
(Fig. 1) DC Output Load Circuit
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
870
Parameter
Parameter
CAS Latency=3
CAS Latency=2
3.3V
1200
50pF
*2
t
t
t
t
t
t
Symbol
t
t
t
RAS(max)
t
t
RRD(min)
RCD(min)
t
RAS(min)
CCD(min)
MRS(min)
V
V
RDL(min)
CDL(min)
BDL(min)
RC
CC(min)
RP(min)
OH
OL
CL
(
min
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
)
DD
= 3.3V 0.3V
5.5
10
3
3
3
7
-C
2
-
-
-
-
-
OL
- 7 -
OH
= 2mA
= -2mA
10
*2
3
6
3
3
7
, T
-6
A
2
= 0 to 70 C)
-
-
-
-
-
tr / tf = 1 / 1
See Fig. 2
2.4 / 0.4
Value
Version
10
1.4
1.4
3
7
3
3
7
Output
100
-7
2
1
1
1
1
2
2
1
8.7
2
2
2
5
7
3
8
3
3
6
9
(Fig. 2) AC Output Load Circuit
-8
10
2
2
2
5
7
Z0=50
10
3
2
2
5
7
-10
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
12
2
2
2
4
6
Unit
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ns
us
ea
Vtt=1.4V
Unit
50
ns
50pF
V
V
V
Note
*1
2, 5
1
1
1
1
1
2
2
4