km416s1120d ETC-unknow, km416s1120d Datasheet - Page 3

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

KM416S1120D
512K x 16Bit x 2 Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
FUNCTIONAL BLOCK DIAGRAM
clock
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
- 3 -
KM416S1120DT-G/FC
KM416S1120DT-G/F6
KM416S1120DT-G/F7
KM416S1120DT-G/F8
KM416S1120DT-G/F10
GENERAL DESCRIPTION
Latency & Burst Length
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Programming Register
WE
The KM416S1120D is 16,777,216 bits synchronous high data
Data Input Register
Column Decoder
512K x 16
512K x 16
Part NO.
L(U)DQM
LWCBR
*
Samsung Electronics reserves the right to
change products or specification without
notice.
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
LDQM
Interface Package
LVTTL
DQi
LWE
LDQM
TSOP(II)
50